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SOLID-STATE IMAGING ELEMENT AND SIGNAL READING METHOD THEREOF

外国特許コード F070001667
整理番号 F070001667
掲載日 2007年9月14日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2006JP311313
国際公開番号 WO 2007/000879
国際出願日 平成18年6月6日(2006.6.6)
国際公開日 平成19年1月4日(2007.1.4)
優先権データ
  • 特願2005-189314 (2005.6.29) JP
発明の名称 (英語) SOLID-STATE IMAGING ELEMENT AND SIGNAL READING METHOD THEREOF
発明の概要(英語) After resetting a potential (VPD) of a photodiode (11) to a prescribed potential (VRST), light is permitted to enter the photodiode (11) for a prescribed period, and the VPD is reduced by a quantity corresponding to the light entered. Then, when a falling ramp voltage (VRAMP) is applied to a source terminal of a first transistor (12), i.e. a source grounding type amplifier for reading VPD, the MOS transistor (12) is turned on and the output is rapidly reduced when a voltage difference between a gate and a source of the MOS transistor (12) exceeds a threshold voltage. When a signal having a pulse width from a ramp voltage sweep start point to an output rapid drop point is generated by a comparator circuit (4), the pulse width corresponds to the quantity of the light entered. When such PWM system signal reading is performed, power consumption is reduced while ensuring a dynamic range, and furthermore, a high pixel rate can be achieved by reducing the pixels.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • National University Corporation Nara Institute Of Science And Technology
  • 発明者(英語)
  • Kagawa, Keiichiro
  • Ohta, Jun
国際特許分類(IPC)
指定国 AE AG AL AM AT AU AZ BA BB BE BF BG BJ BR BW BY BZ CA CF CG CH CI CM CN CO CR CU CY CZ DE DK DM DZ EC EE EG ES FI FR GA GB GD GE GH GM GN GQ GR GW HR HU ID IE IL IN IS IT JP KE KG KM KN KP KR KZ LC LK LR LS LT LU LV LY MA MC MD MG MK ML MN MR MW MX MZ NA NE NG NI NL NO NZ OM PG PH PL PT RO RS RU SC SD SE SG SI SK SL SM SN SY SZ TD TG TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
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