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Field-effect transistor with spin-dependent transmission characteristic with half-metal source and drain

外国特許コード F110004006
整理番号 K02006EP
掲載日 2011年7月7日
出願国 欧州特許庁(EPO)
出願番号 04704734
公報番号 1603168
公報番号 1603168
出願日 平成16年1月23日(2004.1.23)
公報発行日 平成17年12月7日(2005.12.7)
公報発行日 平成29年1月11日(2017.1.11)
国際出願番号 JP2004000567
国際公開番号 WO2004079827
国際出願日 平成16年1月23日(2004.1.23)
国際公開日 平成16年9月16日(2004.9.16)
優先権データ
  • 特願2003-062453 (2003.3.7) JP
  • 特願2003-164398 (2003.6.9) JP
  • 2004WO-JP00567 (2004.1.23) WO
発明の名称 (英語) Field-effect transistor with spin-dependent transmission characteristic with half-metal source and drain
発明の概要(英語) (EP1603168)
When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region.
However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source (3a).
That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source (3a).
If the ferromagnetic source (3a) and the ferromagnetic drain (5a) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current.
Contrarily, if the ferromagnetic source (3a) and the ferromagnetic drain (5a) are antiparallel magnetized, up-spin electrons cannot be conducted through the ferromagnetic drain (5a) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain (5a).
Thus, a high-performance high-degree of integration non-volatile memory composed of MISFETs operating on the above operating principle can be fabricated. <IMAGE> <IMAGE>
特許請求の範囲(英語) [claim1]
1. A transistor using spin-polarized conduction carriers comprising: a ferromagnetic source (3a) made of a half metal , such as a Heusler alloy like Co 2MnSi, zinc-blende CrAs, CrSb and MnAs, exhibiting a metallic band structure for one of the spins , called metallic spin band, while exhibiting a semiconductor-like or insulator-like band structure for the other spin , called semiconductor spin band, the half metal being a ferromagnetic body, configured such that in operation spin-polarized conduction carriers are injected from the ferromagnetic source; a ferromagnetic drain (5a) made of a half metal and configured such that in operation it receives the spin-polarized conduction carriers injected from the ferromagnetic source (3a); and a semiconductor layer (1) that is provided between the ferromagnetic source (3a) and the ferromagnetic drain (5a), and is joined to the ferromagnetic source (3a) and the ferromagnetic drain (5a); a gate electrode (7) associated with the semiconductor layer (1); and contacts (3b, 5b) made of a non-magnetic metal or a non-magnetic conductor contacting the ferromagnetic source (3a) and the ferromagnetic drain (5a), wherein the ferromagnetic source (3a) and the ferromagnetic drain (5a) form Schottky junctions having a Schottky barrier at the interface between the semiconductor layer (1) and the metallic spin band in the respective half metal; and wherein, the Fermi energy of the non-magnetic contacts (3b, 5b) is at an energy level that falls within the band gap of the semiconductor spin band of the ferromagnetic source (3a) and the ferromagnetic drain (5a).
[claim2]
2. The transistor as claimed in claim 1, further comprising a metal layer (23a, 25a) or another semiconductor layer formed between the ferromagnetic source (3a) and the semiconductor layer (1) and between the ferromagnetic drain (5a) and the semiconductor layer (1).
[claim3]
3. The transistor as claimed in claim 1, wherein the semiconductor layer is an n-type semiconductor layer (1), and a difference between the Fermi energy (E F) and an energy (E C **HM) of a bottom of a conduction band of the semiconductor spin band is greater than a height ( [GREEK PHI SYMBOL] n) of the Schottky barrier formed between the metallic spin band and the semiconductor layer (1).
[claim4]
4. The transistor as claimed in claim 1, wherein the semiconductor layer is a p-type semiconductor layer (1), and a difference between the Fermi energy (E F) and an energy (E V **HM) of a top of a valence band of the semiconductor spin band is greater than a height ( [GREEK PHI SYMBOL] p) of the Schottky barrier formed between the metallic spin band and the semiconductor layer (1).
[claim5]
5. The transistor as claimed in any of claims 1 to 4, wherein the semiconductor spin band of the half metal has a wider band gap than the band gap of the semiconductor layer (1).
[claim6]
6. The transistor as claimed in any of claims 1 to 5, wherein a channel length, that is defined as the length in the carrier conducting direction in the semiconductor layer (1) or the distance between the ferromagnetic source (3a) and the ferromagnetic drain (5a), is so short that the semiconductor layer (1) conducts carriers in a ballistic manner, or the channel length is equal to or shorter than the mean free path associated with carrier energy relaxation.
[claim7]
7. A memory device comprising the transistor as claimed in any of claims 1 to 6,
the transistor arranged to store information in accordance with the relative magnetization direction of the ferromagnetic drain (5a) with respect to the ferromagnetic source (3a),
the information stored in the transistor being detected based on the trans-conductance of the transistor depending on the relative magnetization direction of the ferromagnetic drain (5a) with respect to the ferromagnetic source (3a).
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • SUGAHARA SATOSHI
  • TANAKA MASAAKI
国際特許分類(IPC)
欧州特許分類/主・副
  • B82Y010/00
  • G11C011/16
  • H01L027/22M4F
  • H01L029/66S
指定国 (EP1603168)
Contracting States: DE FR GB
参考情報 (研究プロジェクト等) PRESTO Nanostructure and Material Property AREA
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