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Optically reconfigurable gate array write state inspection method, write state inspection device, and optically reconfigurable gate array

外国特許コード F110004652
整理番号 RX05P10WO
掲載日 2011年7月20日
出願国 中華人民共和国
出願番号 200580027484
公報番号 101015123
公報番号 101015123
出願日 平成17年6月16日(2005.6.16)
公報発行日 平成19年8月8日(2007.8.8)
公報発行日 平成22年8月25日(2010.8.25)
優先権データ
  • 特願2004-181913 (2004.6.18) JP
発明の名称 (英語) Optically reconfigurable gate array write state inspection method, write state inspection device, and optically reconfigurable gate array
発明の概要(英語)

There is provided a write state inspection technique not requiring a circuit dedicated to a write state inspection of inside of a logical circuit of the ORGA. An optical signal pattern configures the logical circuit structure in the ORGA as follows: when an optical signal irradiated to the optically reconfigurable bit element to be inspected is switched from ON to OFF, at least one logical level or output impedance is changed. A first and a second optical signal pattern in which an optical signal irradiated to the optically reconfigurable bit element to be inspected is ON or OFF are successively irradiated/inputted to the logical circuit.

Together with this, each of the output states is detected by an output state detection circuit connected to the respective logical output terminals and detecting whether the logical level of the output terminal is at H level, L level, or high impedance. The state detected is compared to the normal output state of the inputted optical signal pattern so as to judge whether the information write state by the optical signal for each optically reconfigurable bit element is successful.

  • 出願人(英語)
  • JAPAN SCIENCE & TECH AGENCY
  • 発明者(英語)
  • WATANABE MINORU,KOBAYASHI FUMINORI
国際特許分類(IPC)
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