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Field-effect transistor with spin-dependent transmission characteristic and nonvolatile memory using same

外国特許コード F110004844
整理番号 K02006KR
掲載日 2011年7月22日
出願国 大韓民国
出願番号 20057016587
公報番号 20050106497
公報番号 100681379
出願日 平成17年9月6日(2005.9.6)
公報発行日 平成17年11月9日(2005.11.9)
公報発行日 平成19年2月12日(2007.2.12)
国際出願番号 JP2004000567
国際公開番号 WO2004079827
国際出願日 平成17年9月6日(2005.9.6)
国際公開日 平成16年9月16日(2004.9.16)
優先権データ
  • 特願2003-062453 (2003.3.7) JP
  • 特願2003-164398 (2003.6.9) JP
発明の名称 (英語) Field-effect transistor with spin-dependent transmission characteristic and nonvolatile memory using same
発明の概要(英語) When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region.
However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source (3a).
That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source (3a).
If the ferromagnetic source (3a) and the ferromagnetic drain (5a) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current.
Contrarily, if the ferromagnetic source (3a) and the ferromagnetic drain (5a) are antiparallel magnetized, up-spin electrons cannot be conducted through the ferromagnetic drain (5a) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain (5a).
Thus, a high- performance high-degree of integration nonvolatile memory composed of MISFETs operating on the above operating principle can be fabricated.
特許請求の範囲(英語) [claim1]
1. Spin-polarized transport carrier (hereinafter referred to as spin polarization pole conducting career. ) Comes from a ferromagnetic metal to inject Alfonso, (hereinafter referred to as "strong magnetic Alfonso,". ) And the

Drain be from ferromagnetic spin polarization is injected from the strong magnetic source extremely affected by conduction Kiya RIA (hereinafter referred to as "strong magnetic drain". ), Was established between the above strong magnetic source and wherein strong magnetic drain the interface for each of the above strong magnetic source and wherein strong magnetic drain out Si semiconductor layers that form with Oti 1 barrier Schottky junctions 1 and

Gates said semiconductor layer for electrodes

Transistors.

2, wherein said strong magnetic source or strong magnetic wherein Drake and the direction of magnetization reversal of to by said strong magnetic sources said strong magnetic drain relative magnetization direction is the direction (hereinafter referred to as "parallel magnetic". ) Or opposite directions (hereinafter referred to as "antiparallel magnetization". ) To the billing features to control the scope paragraph 1 stated transistor.
[claim2]
3. Said strong magnetic source and wherein strong magnetic drain to the range of claims that have been formed due to ferromagnetic metal to paragraph 1 or paragraph 2 above stated transistor.
[claim3]
4. conduction type of spin polarized pole carrier wherein the same semiconductor layer and (hereinafter called "storage channel" and. ), Wherein spin polarization pole transmission waveguide Kiya RIA arises in the case of electronic conduction Pando side wherein Schottky barrier, said spin polarization pole conductivity iyal a hole in the above shot key barriers's claim that expensive electronic Pan de side to feature scope article

(1) paragraphs (1) to (3) either the stated transistor.
[claim4]
5. wherein spin polarization pole carrier conduction type semiconductor layer and different (hereinafter called "inverted channel" and. ) In the TC wherein Schottky barrier cases are not formed by the inversion layer in the semiconductor layer, causing expensive electronic Pando side wherein histones Act key barriers in the case of electronic wherein spin polarization pole conductivity Kiya re!, said spin polarization pole carrier if the hole is Van (1) any feature claims that de-side range (1), paragraph (3) of the stated transistor.
[claim5]
6. wherein accumulation channel type in the previous game, wherein said spin polarization pole conduction Kiya re o in the State between electrode and wherein strong magnetic source and do not apply voltage to the Chopin by TK 1 barrier semiconductor layer to the tunnel and. in paragraph 4 of the scope of claims to be injected by bi熱 emission characteristics stated transistor.
[claim6]
7. Wherein conduction kiyaria polar said strong magnetic source wherein spin polarization in _said_ storage channel wherein gate electrode shorted to be more at the interface between a semiconductor layer and strong magnetic source said shouji claims to be injected by tunneling through TK 1 barrier in a semiconductor layer to the range (4) or (6) transistors in.
[claim7]
8. Circumstances wherein accumulation channel type in _said_ gate electrode do not apply voltage to wherein spin polarization pole conductive kiyaria, wherein shopping Toki by 1 barriers injection due to the semiconductor layer of thermal emission is suppressed, but said strong magnetic source wherein spin-polarized pole wherein conduction kiyaria claims characterized by tunnelling through the shopping keys barriers semiconductor layer to inject the scope paragraph 4 stated transistor.
[claim8]
9. Wherein said accumulation channel type in _said_ gate electrode shorted to by said strong magnetic source wherein spin polarization pole carrier said at the interface between a semiconductor layer and strong magnetic source shouji claims characteristics can be controlled based on the tunneling through a network key barriers, arise between such strong magnetic source and wherein strong magnetic drain current range (4) or paragraph (8) described transistors.

1 0. Not shorted during wherein said reverse channel type in _said_ gate electrode and above strong magnetic sources state, wherein shouji by TK 1 barrier, wherein said spin polarization pole conductivity kiyaria claims to be injected by tunnel to the semiconductor layer and heat release to feature the scope paragraph 5 stated transistor.

1 1. On wherein said reverse channel type in _said_ gate electrode voltage may be applied to that pin eccentric pole conductivity Kiya RIA 記su said strong magnetic source before, if the inversion layer at or above Semiconductor is heat emission or tunnel at least a claim to it than by injection into semiconductor layer wherein range (5) or paragraph 1 0 transistors in.

1 2. Claims to be under wherein said reverse channel type in _said_ gate electrode do not apply voltage to the formed inversion layer said semiconductors, said strong magnetic source wherein spin-polarized pole carrier heat emission or tunnel but at least by injection into semiconductor layer wherein range (5) at the stated transistor.

1 3. The above inversion channel type in _said_ gate electrode voltage may be applied to that, said strong magnetic source wherein spin-polarized pole carrier from such strong magnetic source semiconductor layer to heat release or tunnel less on at least one claims characteristics can be controlled based on injected and wherein strong magnetic source and wherein strong magnetic drain between the current range (5) or paragraph 2 stated transistor.

1 4. Wherein said accumulation channel or above inversion channel type, ' half wherein spin polarization pole carrier injected in the conducting layer is to claim that spin polarization dependent spin polarization said strong magnetic source fenolemi energy that characterized range (4) 1 ternary one Chronicle described transistors.

1 5. Wherein said storage channel or in the above-mentioned inverted channel wherein strong magnetic source and wherein strong magnetic drain with electrical resistance, said strong magnetic source and wherein strong magnetic drain and relative magnetization direction is antiparallel magnetization by spin-dependent scattering above spin polarization pole conductivity Kiya RIA said strong magnetic drain if it is injected from the previous strong magnetic source be parallel magnetization by magnetization relative to _said_ spin-polarized ultra small electrical resistance due to conduction kya RIA said strong magnetic drain spin-dependent scattering large when Many will claim to that extent (4) until the 1 4 paragraph one paragraph stated transistor.

1 6. Under the same paiasu to said strong magnetic source and wherein strong magnetic Dre Inn and relative magnetization direction can be controlled or transfer are billing features to range (1) 1 paragraph 5 until the one in transistors in.

1 7. Wherein said storage channel or, if said strong magnetic source and wherein strong magnetic drain has a parallel magnetic wherein inverted channel in the above game one, the voltage applied to the electrodes and wherein strong magnetic source and strong magnetic wherein drei, with invoice feature to have a threshold that is defined as the gate voltage rise determined during the current range (4) 1 paragraph one paragraph stated transistor.

1 8. Pando structures in metal to spin while the ferromagnetic (hereinafter "referred to a metallic Spin Pando J. ), To the spin of the other is Pan de structure semiconductor or insulator (below, "semiconductor spin van de" and surname. ) And strong magnetic sources into RIA-take the spin-polarized transport Kiya

And the strong magnetic drain consisting of subjected to spin-polarized wherein conduction kya RIA infused into the strong magnetic source chef me Tal

Been established between such strong magnetic source and wherein strong magnetic drain and said strong magnetic source and strong magnetic wherein Drake, of semiconductor layer bonded with each and

Gates said semiconductor layer for electrodes

Transistor characteristic to have.

1 9. Wherein said chef meta Le metal a Su Ping Pando said strong magnetic source and wherein strong magnetic drain in the interface between a semiconductor layer SI claim form with Oti 1 barrier Schottky junctions 1 to range 1 paragraph 8 to the stated transistor.

2 0. Wherein carrier conduction type semiconductor layer and the same (hereinafter called "storage channel" and. ), Wherein transport carrier in the case of the electronic conduction is due wherein a metallic r Pimpin de wherein Schottky barrier 1 van de side, wherein transport carrier if the hole is caused by wherein a metallic Spin Pando said Schottky barrier 1 Valence electron Pando side that claims to feature scope paragraph 1 of 8 or 9 (1) of electrical
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • SUGAHARA SATOSHI
  • TANAKA MASAAKI
国際特許分類(IPC)
参考情報 (研究プロジェクト等) PRESTO Nanostructure and Material Property AREA
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