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Reconfigurable logical circuit using transistor having spin-dependent transmission characteristic

外国特許コード F110004847
整理番号 K02010KR
掲載日 2011年7月22日
出願国 大韓民国
出願番号 20057017848
公報番号 20050111398
公報番号 100789044
出願日 平成17年9月23日(2005.9.23)
公報発行日 平成17年11月24日(2005.11.24)
公報発行日 平成19年12月26日(2007.12.26)
国際出願番号 JP2004004379
国際公開番号 WO2004086625
国際出願日 平成17年9月23日(2005.9.23)
国際公開日 平成16年10月7日(2004.10.7)
優先権データ
  • 特願2003-086499 (2003.3.26) JP
発明の名称 (英語) Reconfigurable logical circuit using transistor having spin-dependent transmission characteristic
発明の概要(英語) A nonvolatilely reconfigurable logical circuit is built.
It is a reconfigurable logical circuit based on the CMOS configuration using the spin MOSFET.
By changing the transmission characteristic of each transistor in accordance with the magnetization states of Tr1, Tr2, Tr5, and Tr8 which are spin MOSFETs, it is possible to reconfigure all the two-input symmetric functions AND/OR/XOR/NAND/NOR/XNOR/"1"/"0".
Since it is possible to constitute the logical function by a small number of nonvolatile elements, it is possible to reduce the chip area, thereby increasing the speed and reducing the power consumption.
特許請求の範囲(英語) [claim1]
1. In circuits with transmission characteristics depend on the orientation of the spin transfer kiyaria spin train register that contains the

To reconfigure the function by changing the operating points based on transmission characteristics of the said spin transistor to change by changing the above conductivity kiyaria spin this and circuits that can be.
[claim2]
2. ... Contains a least two layers of ferromagnetic layer, wherein ferromagnetic body layer of magnetization on circuit is changing the operation point by varying the magnetization State of the previous spin transistors, circuits including the spin transistor having a transmission in which the feature can be.
[claim3]
3. wherein spin transistor is independent control of direction of magnetization in ferromagnetic (called a free layer in the following. ), Do not change the direction of magnetization in ferromagnetic materials (hereinafter,

Referred to as pin layer. ) And has at least one at a time, said Frito and further State has a PIN layer and the direction of magnetization ("parallel magnetic" as referred to below. ) And the magnetization be opposite each other with the second State (hereinafter referred to as "antiparallel magnetization". ), And the features make reformulation and changing the operating points based on the magnetization State of the two claim to that extent paragraph 2 circuits described in.
[claim4]
4. Has to discharge the terminals 1 to charge the first Terminal, Terminal No. 1 point of said behavior and output circuit group and the first 2 networks and, on the other hand is one circuit of the first and second networks is not in any claims to contain both said spin transistor range (1), paragraph (3) of paragraph mentioned circuit.
[claim5]
5. Said spin transistor kiyaria spin polarization or magnetization on billing features to determine the potentials of the first terminal by controlling the propagation of existing scope paragraph 4 circuits described in.
[claim6]
6. Weighted by the capacitance of the capacitor connecting common to more than one input and the input floating gate and neural network that contains a y M O S (hereinafter, referred to asv M O S. ) Based on the signal through a structure under range on request to output the signal to paragraph (1) to paragraph (5) is in either paragraph (1) circuits described in.
[claim7]
7. each of the plurality of input signal equal stands to be weighted are you claim to that extent paragraph 6 circuits described in.
[claim8]
8. in paragraph 1 of any billing features to enforce the potentials in the terminal of the first to isolate and logic 0 and logic level output logic thresholds to reflect above spin transistor propagation characteristics of the above points-range (4) paragraph (7) of the circuits described.
[claim9]
9. circuit with logical threshold stipulated any scope of paragraph (1), paragraph (8) (1) located on the output terminals of the circuit of the AZD converter is connected to features.

1 0. Said spin transistor includes MO S structure and ferromagnetic material, consists of is MO S F E T-spintrungis Ta consists of source and drain the happiness (below "style and spin MO S F ETj) in (1) any claim to that extent (1) paragraph (9) of the circuits described in.

1 1 1 conductive type MO S F E T or 1 conductive type spin MO S F E T and first conductivity type and same conductive type MO S F E T or first conductivity type and same conductive type spin MO S F E T and the range request feature to each circuit of the first and second networks contained in paragraphs 3 through 9 one paragraph circuits described in.

1 2. Circuit group mentioned in part 2 with the source included in the circuit of the first enhancements-MO S F ET or enhancement-type spin MO S F ET including rare and drain are enhancement-MO S F ET or enhancement-type spin M O S F ET containing e/e circuit with Terminal connected structure and connections, formed one of the first to feature to feature request-scope (3) 1 paragraph one paragraph mentioned circuit.

1 3. Circuit group configured _said_ EZE circuit first enhan do-MO S F E T or enhancement-type spin M ○ claim to being connected to the gate of the enhancement-type MO S F E T or the enhancement-type spin MO S F E T S F E T de lane range 1 paragraph 2 of the mentioned circuit.

1 4-enhan do-MO S F E T contained in the circuit group configured _said_ circuit EZE second or enhancement-type spin M ○ S F E T, vMO S structure has a claim to that extent paragraph 1 of 2 ' or section 1 (3) circuit.

1 5. Depletion-type MO S F E T included in the circuit of the first or de pre... included in the circuit group mentioned in part 2 of session type spin MO S F E T source enhancement type MO S F E T or enhancement-type spin MO S F ET drain and on request including e/d circuit with Terminal connected structure and connections, formed one of the first to feature the scope paragraphs 3 1 paragraph one (1) circuits described in.

1 6-depress in the circuit group configured _said_ e/d circuit first SI 3 and advanced payment claims that the source of the type MO S F E T or debrezion type spin MO S F E T is connected to the gate of the depression-MO S F E T or the depression-type spin MO S F ET range 1 section 5 of the circuits described in.

1 7. Circuit group configured _said_ e/d circuit wherein said second enhan do-MO S F E T or enhancement-type spin MO S F E T

Claims V MO S structure and characteristics of range, 1 paragraph 5 or paragraph 6 of circuit.

1 according to the 8 capacitors 2 inputs are weighted by the capacitance (hereafter, each of its inputs to A and B. ) To input the wherein MO S structure of this ' and feature requests ranges 1 paragraph 1 from paragraph (1) or paragraph 1 of the circuits described in.

1 9. N AND/NO R reconfigurable logic circuit that contains the input to the terminal of the first circuit from the request scope (4) 1 paragraph 8 to the one described in paragraph (1) above a/d converter to feature or AN DZOR reconfigurable logic circuit.

2 0. The first and second networks or circuits of the first or second

Said spin the E T F MO S another spin MO S F E T source or drain connects to the terminal of the first, and only with specific input the wherein different spin MO S F E T on the different spin MO S F E T-gate ' in paragraph (1) of the request that contains the circuitry controlling the potential of the first terminal by connecting the level / Recht circuits to range 1 paragraph 1 from 1 paragraph 9 to the one in circuit.

2 1. Circuit group mentioned in part 2 of the

A common source to the terminal of the first n-channel type wherein different spin M ○ S F E T drain connects the n-channel type wherein another spin MO S F E T the game-g. to input A = B = "0″ only η channel type of the different spin M ○ claims to contain the circuitry controlling the potential of the first terminal by connecting the circuitry to turn S F ET range 1 paragraph 1 from (2 0) until the one in above described circuitry.

2 2. The first circuit group

And connect the p-channel type in the terminal of the first source is connected to the power supply voltage above another spin MO S F E T drain, at the gates of the channel type of the different spin M O S F E T input A = B = "1" if only ρ channel type of art from (J spin M ○ claims to contain the circuitry controlling the potential of the first terminal by connecting the circuitry to turn S F E-range 1 paragraph 1 from 2 paragraph one paragraph mentioned circuit.

2 3. Said circuitry is billing features to EZE, e/d or CMO's consist in Val data by range, 0 paragraph 2 from (2-3) in the paragraph (1) or circuits described in.
[claim10]
24. wherein a/d converter to input terminal of the first circuit request scope paragraph 2 of 0 from 3 paragraph 2 from the one described in paragraph (1) reformulation possible logical circuits.

2 5. Have the above-mentioned AZD Converter output to input, inverter

Symmetrical demand range 0 paragraph 2 or paragraph 2 4 total 2 input of reconfigurable logic circuit can function.

2 6 1 conductive type MO S F E T or 1 conductive type spin MO S F E T and first second conductive type and different conductivity type of MO S F E T or a second conductivity type of speaker, MO S F et (1) any claims to features in each circuit of the first circuit group, Yopi said second range (3), paragraph (9) of the circuits described in.

2 7. Features claims that CMO S circuit with Terminal 1 was formed wherein drain pins connected the drain pin included in the circuit of the first p-channel MO S F E T or p a receiver type pin MO S F E T and included in the circuit group mentioned in part 2 of n-channel MO S F E T or n minimizing type spin M O S F ET each other to a common structure and common range, paragraph 2 of 6 on the circuits described.

2 8. Claims that CMO S configuration circuits in the circuit of the first p-channel spin MO S F E T with n-channel spin MO S F E T contained in the circuit of the second to feature scope paragraph 2 of 6 in the circuits described in. 2 9. Configured _said_ CMO S circuit wherein p virtual type MO S F E T or previous p-channel spin M O S F E T and wherein n minimizing type M O S F E T or previous n-channel spin MO S F E T v MO S structure of common off rating GE one invoice feature to have a scope paragraph 2 of 6 from the 2.

In paragraph (1) to (8) or circuits described in.

3 0... claims to feature the input of two weighted by the capacitance of the capacitor (below, to each of its inputs A and B) to input the wherein V MO S structure scope paragraph 2 of 9 in the circuits described in.

3 1. AND/OR reconfigurable logic feature to include in request scope paragraph 2 of 6 from the 3 0 paragraph from the one described in paragraph (1) above the first pin to the input a/d converter or N-AND/NOR reconfigurable logic circuit.

3 2. Wherein first and second networks or circuits of the first or second input connects to the first Terminal, said spin the E T F MO S different for another spin MO S F E T's source or drain, gate of spin S F E MO wherein different only by the spin] be on the VIO S F E T to from paragraph 26 of the range of claims including-御su circuits first Terminal voltage by connecting the circuitry to feature 3 paragraph either and or paragraph (1) circuits described in.

3 3. Circuit group mentioned in part 2 of the

In paragraph 1 request that contains the circuitry to control the first Terminal voltage can be connected and connect the grounded Terminal first, source n-channel type wherein spin MO S F ET in drain, only on "0" turn n-channel type of the different spin Tora electrical input A = B = n-channel type of the different spin transistor gate circuitry to feature scope paragraph 2 of 6 from the 3 binary or circuits described in.
[claim11]
34. include a range of claims paragraph 26 3 ternary one (1) to input terminal of the first circuit of AZD converter features.. ANDZORZXNOR reconfigurable logic circuit or NANDZNORZX OR reconfigurable logic circuit. -3 5. The first circuit group

Range request that contains the circuitry controlling the potential of the first terminal by connecting the level shift circuit and connect the p-channel type in the terminal of the first source is connected to the power supply voltage above spin MO S F ET of the drain, at the gates of the p-channel type of the different spin M O S F E T input A = B = "1" only in p-channel type of the spin MO S F ET turn to feature article

2 6 paragraph 5 paragraph 3 to the one mentioned in paragraph (1) of the circuit. ·

3 6. That contains the claim scope paragraph 26 3 paragraph 5 until the one (1) to input terminal of the first circuit of a/d Converter 1 characteristics shall ANDZOR XOR reconfigurable logic circuits or N AND/NOR/XN OR reconfigurable logic circuit.

3 7. Have the impact, wherein AZD Converter output to input and demand scope paragraph 2 of 6 from the 3 paragraph one paragraph listed all logic circuits 2 inputs symmetric functions.

3 8. Characteristics and controlling the potential of the first terminal by connecting the circuitry, and connect to a common source to the terminal of the first n-channel type wherein different spin MO S F E T drain n-channel type of the different spin MO S F E T gate inputs A = B = 1 If n-channel type of the different spin MO S F E T turn

To claim the networks controlling the potential of the first terminal by connecting the p-channel type of the different spin MO S F E T gate inputs A = B = 0 if p-channel type of the spin MO S F ET turn, and then connect the drain p-channel type in the terminal of the first source is connected to the power supply voltage above spin M O S F E T differs from another spin M O S F ET Les eat no reshift circuit features a range, 6 paragraph 2 or paragraph 3 of circuit.

3 9. Claims range 3 paragraph 8 to the first circuit in Terminal and type shall have a/d converter for all features including 2 inputs symmetric function logic.

4 0. Said circuitry is e/e or E-D or C M O S Inn billing features to consist of many 1 range 3 paragraph 2 from 9 paragraph 3 until the are to either (1) circuits described in.

4 1. Consists of CMO S inverter, wherein CMO S inverter p Frost Nell-MO S F E-or n-channel M O S F E T on the other hand, also are both p-channel MO S F ET and n minimizing type M O S F E T speaker, AZD converter features to MO S F E t.

4 2. Claims can be logical threshold wherein spin MO S F ET of magnetization by a variable range 1 paragraph 4 a of a/d converter.

4 3. Connect and AZ D converter can be said logic threshold circuits with an analog output stage, variable, you can reconfigure the logical functions logical circuits.
[claim12]
44. move operation point by varying the transfer characteristics of the previous transistor circuits containing transistors with variable transmission and to refine the features this and circuits that can be.

4 5. Scope of paragraph (1) No. 1 section 4 paragraph (4) of any circuits described including including integrated circuits.
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • SUGAHARA SATOSHI
  • MATSUNO TOMOHIRO
  • TANAKA MASAAKI
国際特許分類(IPC)
参考情報 (研究プロジェクト等) PRESTO Nanostructure and Material Property AREA
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