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Field Effect Transistor and Method for Manufacturing Same 新技術説明会

外国特許コード F110004848
整理番号 K02011WO
掲載日 2011年7月22日
出願国 大韓民国
出願番号 20067002013
公報番号 20060037411
公報番号 100801544
出願日 平成18年1月27日(2006.1.27)
公報発行日 平成18年5月3日(2006.5.3)
公報発行日 平成20年2月12日(2008.2.12)
国際出願番号 JP2004010696
国際公開番号 WO2005010974
国際出願日 平成18年1月27日(2006.1.27)
国際公開日 平成17年2月3日(2005.2.3)
優先権データ
  • 特願2003-281104 (2003.7.28) JP
発明の名称 (英語) Field Effect Transistor and Method for Manufacturing Same 新技術説明会
発明の概要(英語) Disclosed is a field effect transistor comprising an SiC substrate (1), a source (3a) and a drain (3b) formed in the surface of the SiC substrate (1), an insulating structure including an AlN layer (5) which is formed in contact with the SiC surface and has a thickness not less than a single-molecule layer and an SiO2 layer formed on the AlN layer, and a gate electrode (15) formed on the insulating structure.
In such a field effect transistor, it is possible to suppress leakage current, while forming a good interface with the Sic surface.
特許請求の範囲(英語) [claim1]

[1] SiC surface structure and

The SiC surface structure formed the source and drain, and

Interface control layer formed by m of nitride layer of si layer thickness beyond touching wherein sic surface structure and the surface layer and insulation structure and insulation layer formed by materials on the above interface control layer and the different materials the carrier conduction band offset larger than the previous interface control layer

Gate electrode formed on the insulating structure

Field-effect transistors.

[2] SiC surface structure and

The SiC surface structure formed the source and drain, and

Touching the above SiC surface structure formed, including A1 and N and thickness is 1 molecular layer interface on your layer with the interface control layer and insulation structure and insulation layer formed by materials on the above interface control layer and the different materials the carrier conduction band offset larger than the previous interface control layer

Gate electrode formed on the insulating structure

Field-effect transistors.

[3] wherein interface control layer containing A1N layer thickness power nm to claim one or 2 listed in field-effect transistors.

[4] wherein interface control layer of the B, Al, Ga, In at least one or more and 3 any claim 1 characterized to include group III elements and N in force paragraph 1 in field-effect transistors.

[5] wherein interface control layer in-plane lattice constant is SiC in-plane lattice constants and 0. Containing less than 5% have BA1N layers to claim 1 or 2 in field-effect transistors

[6] wherein insulating SiO 2 layer and are selected from the group consisting of Si N-tier and Al 2 O 3 layers of small, from claim 1 characterized that contains 1 layer at least five one in force paragraph 1 described electric field effect ί

[7] wherein insulating layer A1N, A1 and Al N and AlAs and A1N As 1 ― and from consisting of out of power options, is formed by oxidation of deposits of at least one of Al 2 ○ three-tier or small A1 2 containing at least one of the N quantities, or As one of ○ claims to feature three-tier

In paragraph 1 from 1 up to 5 either in field-effect transistors.

[8] wherein insulator having multilayer films formed by multiple dielectric characteristics shall that claims 1 to 7 any, paragraph (1) in the mentioned field-effect transistor.

[9] SiC surface structure and

Interface control layer structure formed by SiC surface structure on touching SiC surface formed including A1 and N, with a thickness of more than 1 first insulation barrier layer and layer formed by a metal or semiconductor, and 2 insulating barrier on the gate electrode layer floating gate structures and

Sources said SiC surface structure formed by adjacent to the floating gate structure and drain layers

Non-volatile memory devices have.

And the process of preparing the substrate [10] SiC surface structure

Process the source and drain on the SiC surface structure and

Wherein SiC surface structure and surface wherein SiC surface structure of step structure system and sanitize process, including the A1 and N and thickness is 1 molecule layer interface control layer forms, forming the insulation structure of insulating material on the interface control layer wherein interface control layer and the different materials the carrier conduction band offset larger than the previous interface control layer and

And the process of forming gate electrode on the insulation structure

Field-effect transistors with manufacturing methods.
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • SUDA JUN
  • MATSUNAMI HIROYUKI
国際特許分類(IPC)
参考情報 (研究プロジェクト等) PRESTO Nanostructure and Material Property AREA
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