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Tunnel transistor having spin-dependent transfer characteristics and non-volatile memory using the same

外国特許コード F110005383
整理番号 K02009WO
掲載日 2011年9月5日
出願国 アメリカ合衆国
出願番号 55180204
公報番号 20060118839
公報番号 7397071
出願日 平成16年3月30日(2004.3.30)
公報発行日 平成18年6月8日(2006.6.8)
公報発行日 平成20年7月8日(2008.7.8)
国際出願番号 JP2004004512
国際公開番号 WO2004088753
国際出願日 平成16年3月30日(2004.3.30)
国際公開日 平成16年10月14日(2004.10.14)
優先権データ
  • 特願2003-095600 (2003.3.31) JP
  • 2004WO-JP04512 (2004.3.30) WO
発明の名称 (英語) Tunnel transistor having spin-dependent transfer characteristics and non-volatile memory using the same
発明の概要(英語) (US7397071)
A MISFET the channel region of which is a ferromagnetic semi-conductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source (or the ferromagnetic drain, or both the ferromagnetic source and ferromagnetic drain).
As a result, binary information can be stored in the form of the relative magnetization directions, and the relative magnetization directions are electrically detected.
If the magnetism is controlled by the electric field effect of the channel region of a ferromagnetic semiconductor, the current needed to rewrite the information can be greatly reduced.
Thus, the MISFET can constitute a high-performance non-volatile memory cell suited to high-density integration.
特許請求の範囲(英語) [claim1]
1. A transistor comprising: a ferromagnetic semiconductor layer;
a source that injects carriers into the ferromagnetic semiconductor layer;a drain that receives the carriers injected into the ferromagnetic semiconductor layer;
and
a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain,wherein at least one of the source and the drain comprises a tunnel barrier joined to the ferromagnetic semiconductor layer.
[claim2]
2. The transistor as claimed in claim 1, wherein one of the source and the drain is a ferromagnetic source or a ferromagnetic drain that comprises the tunnel barrier (a "non-magnetic tunnel barrier") that is made of a non-magnetic material and is joined to the ferromagnetic semiconductor layer, and an electrode (a "ferromagnetic electrode") that is made of a ferromagnetic material and is joined to the non-magnetic tunnel barrier.
[claim3]
3. The transistor as claimed in claim 1, wherein: the source is a ferromagnetic source;
and
the drain is a non-magnetic drain that comprises the tunnel barrier being a non-magnetic tunnel barrier, and an electrode (a "non-magnetic electrode") that is made of a non-magnetic material and is joined to the non-magnetic tunnel barrier.
[claim4]
4. The transistor as claimed in claim 1, wherein: the drain is a ferromagnetic drain;
and
the source is a non-magnetic source that comprises the tunnel barrier being a non-magnetic tunnel barrier, and a non-magnetic electrode joined to the non-magnetic tunnel barrier.
[claim5]
5. The transistor as claimed in claim 1, wherein the source and the drain each comprise the tunnel barrier being a non-magnetic tunnel barrier, and a ferromagnetic electrode joined to the non-magnetic tunnel barrier.
[claim6]
6. The transistor as claimed in claim 1, wherein: the tunnel barrier is a non-magnetic tunnel barrier;
and
the non-magnetic tunnel barrier is made of a semiconductor that is the base material of the ferromagnetic semiconductor layer.
[claim7]
7. The transistor as claimed in claim 1, wherein one of the source and the drain is a ferromagnetic source or a ferromagnetic drain that comprises the tunnel barrier (a "ferromagnetic tunnel barrier") that is made of a ferromagnetic material and is joined to the ferromagnetic semiconductor layer, and a non-magnetic electrode joined to the ferromagnetic tunnel barrier.
[claim8]
8. The transistor as claimed in claim 1, wherein: the source is a ferromagnetic source;
and
the drain is a non-magnetic drain that comprises the tunnel barrier being a non-magnetic tunnel barrier, and a non-magnetic electrode joined to the non-magnetic tunnel barrier.
[claim9]
9. The transistor as claimed in claim 1, wherein: the drain is a ferromagnetic drain;
and
the source is a non-magnetic source that comprises the tunnel barrier being a non-magnetic tunnel barrier, and a non-magnetic electrode joined to the non-magnetic tunnel barrier.
[claim10]
10. The transistor as claimed in claim 1, wherein the source and the drain are a ferromagnetic source and a ferromagnetic drain each comprising the tunnel barrier being a ferromagnetic tunnel barrier, and a non-magnetic electrode joined to the ferromagnetic tunnel barrier.
[claim11]
11. The transistor as claimed in claim 1, wherein: at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain that comprises the tunnel barrier being a non-magnetic tunnel barrier or a ferromagnetic tunnel barrier;an energy barrier due to the ferromagnetic tunnel barrier or the non-magnetic tunnel barrier is formed at least on the side of the conduction band, when the carriers are electrons;
and
the energy barrier is formed at least on the side of the valence band, when the carriers are holes.
[claim12]
12. The transistor as claimed in claim 1, wherein the ferromagnetic semiconductor layer is formed with a ferromagnetic semiconductor having a semiconductor including magnetic elements.
[claim13]
13. The transistor as claimed in claim 1, wherein: at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain that comprises the tunnel barrier;a ferromagnetic electrode is joined to the tunnel barrier;
and
the ferromagnetic source or the ferromagnetic drain comprises the ferromagnetic electrode that is a ferromagnetic metal, a ferromagnetic semiconductor, or a half-metal ferromagnetic material.
[claim14]
14. The transistor as claimed in claim 1, wherein: at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain that comprises the tunnel barrier being a ferromagnetic tunnel barrier;the ferromagnetic source or the ferromagnetic drain includes an insulating ferromagnetic material as the ferromagnetic tunnel barrier;at least the band edge of the conduction band of the insulating ferromagnetic material is spin-split, when the carriers are electrons;
and
at least the band edge of the valence band of the insulating ferromagnetic material is spin-split, when the carriers are holes.
[claim15]
15. The transistor as claimed in claim 1, wherein: at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain that comprises the tunnel barrier;a ferromagnetic electrode is joined to the tunnel barrier;
and
the ferromagnetic semiconductor employed for the ferromagnetic electrode is a ferromagnetic semiconductor having a semiconductor including magnetic elements.
[claim16]
16. The transistor as claimed in claim 1, wherein: at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain that comprises the tunnel barrier;the tunnel barrier is a non-magnetic tunnel barrier or a ferromagnetic tunnel barrier;a ferromagnetic electrode is joined to the tunnel barrier;
and
the ferromagnetic electrode is a half-metal ferromagnetic material;
and
the non-magnetic tunnel barrier or the ferromagnetic tunnel barrier forms an energy barrier in relation to the metallic spin band of the half-metal ferromagnetic material.
[claim17]
17. The transistor as claimed in claim 1, wherein an insulating layer is interposed between the gate electrode and the ferromagnetic semiconductor layer.
[claim18]
18. The transistor as claimed in claim 1, wherein the transistor is formed on a substrate made of a semiconductor, a substrate having a semiconductor layer formed thereon, or a substrate having an insulating layer formed thereon.
[claim19]
19. The transistor as claimed in claim 18, wherein: the transistor is formed on the substrate;the junction interface of the source and the drain in the vicinity of the gate electrode is substantially perpendicular to the principal surface of the substrate;
and
the flowing direction of the carriers moving from the source to the drain is in a plane substantially parallel to the principal surface of the substrate.
[claim20]
20. The transistor as claimed in claim 18, wherein: at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain that comprises the tunnel barrier;the tunnel barrier is a non-magnetic tunnel barrier or a ferromagnetic tunnel barrier;a ferromagnetic electrode or a non-magnetic electrode is joined to the tunnel barrier;
and
the ferromagnetic electrode or the non-magnetic electrode is separated from the ferromagnetic semiconductor layer and the substrate by the non-magnetic tunnel barrier or the ferromagnetic tunnel barrier.
[claim21]
21. The transistor as claimed in claim 18, wherein: the transistor is formed on the substrate;the junction interface of the source and the drain with the ferromagnetic semiconductor is substantially parallel to the principal surface of the substrate;
and
the flowing direction of the carriers moving from the source to the drain is substantially perpendicular to the principal surface of the substrate.
[claim22]
22. The transistor as claimed in claim 18, comprising:
a stacked structure in which the source, the ferromagnetic semiconductor, and the drain are stacked substantially in parallel with the principal surface of the substrate;
and
a gate insulating film and a gate electrode that are formed on a side surface of the stacked structure.
[claim23]
23. The transistor as claimed in claim 22, wherein a conductive semiconductor layer formed on the substrate serves as a contact layer for the source.
[claim24]
24. Transistors as claimed in claim 22, wherein a conductive semiconductor layer formed on the substrate serves as a common contact layer for the sources of the transistors.
[claim25]
25. The transistor as claimed in claim 18, wherein:
the transistor is formed on the substrate;
the junction interface of the source and the drain with the ferromagnetic semiconductor in the vicinity of the gate electrode is substantially parallel to the principal surface of the substrate;
and
the flowing direction of the carriers moving from the source to the drain is in a plane substantially parallel to the principal surface of the substrate.
[claim26]
26. The transistor as claimed in claim 25, wherein: a structure in which a ferromagnetic semiconductor layer, a non-magnetic tunnel barrier, and a ferromagnetic electrode are stacked in this order, or a structure in which a ferromagnetic semiconductor layer, a ferromagnetic tunnel barrier, and a non-magnetic electrode are stacked in this order is formed on the substrate;a concavity is formed in the substrate, the concavity having a bottom with such a depth as to reach the ferromagnetic semiconductor layer or the inside of the ferromagnetic magnetic semiconductor layer;
and
a gate insulating film and a gate electrode are formed on the inner surface of the concave portion.
[claim27]
27. The transistor as claimed in claim 18, wherein: the source and the drain are a ferromagnetic source and a ferromagnetic drain each comprising the tunnel barrier;an electrode is joined to the tunnel barrier;the electrode is a ferromagnetic electrode in the case that the tunnel barrier is a non-magnetic tunnel barrier, and the electrode is a non-magnetic electrode in the case that the tunnel barrier is a ferromagnetic tunnel barrier;
and
the magnetization configuration between the ferromagnetic semiconductor layer and the ferromagnetic electrode or the ferromagnetic tunnel barrier contained in the ferromagnetic source and the ferromagnetic drain can be adjusted to parallel magnetization or antiparallel magnetization by changing the magnetization direction of the ferromagnetic semiconductor layer, with the magnetization configuration between the ferromagnetic materials contained in the ferromagnetic source and the ferromagnetic drain being fixed to parallel magnetization.
[claim28]
28. The transistor as claimed in claim 18, wherein: the source and the drain are a ferromagnetic source and a ferromagnetic drain each comprising the tunnel barrier;an electrode is joined to the tunnel barrier;the electrode is a ferromagnetic electrode in the case that the tunnel barrier is a non-magnetic tunnel barrier, and the electrode is a non-magnetic electrode in the case that the tunnel barrier is a ferromagnetic tunnel barrier;
and
the magnetization configuration between the ferromagnetic semiconductor layer and the ferromagnetic electrode or the ferromagnetic tunnel barrier contained in the ferromagnetic source and the ferromagnetic drain can be adjusted to parallel magnetization or antiparallel magnetization by changing the magnetization direction of the ferromagnetic electrode or the ferromagnetic tunnel barrier contained in the ferromagnetic source and the ferromagnetic drain.
[claim29]
29. The transistor as claimed in claim 1, wherein: at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain that comprises the tunnel barrier;an electrode is joined to the tunnel barrier;the electrode is a ferromagnetic electrode in the case that the tunnel barrier is a non-magnetic tunnel barrier, and the electrode is a non-magnetic electrode in the case that the tunnel barrier is a ferromagnetic tunnel barrier;
and
the magnetization configuration between the ferromagnetic semiconductor layer and the ferromagnetic electrode or the ferromagnetic tunnel barrier contained in the ferromagnetic source or the ferromagnetic drain can be adjusted to parallel magnetization or antiparallel magnetization by changing the magnetization direction of the ferromagnetic semiconductor layer.
[claim30]
30. The transistor as claimed in claim 1, wherein: at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain that comprises the tunnel barrier;an electrode is joined to the tunnel barrier;the electrode is a ferromagnetic electrode in the case that the tunnel barrier is a non-magnetic tunnel barrier, and the electrode is a non-magnetic electrode in the case that the tunnel barrier is a ferromagnetic tunnel barrier;
and
the magnetization configuration between the ferromagnetic semiconductor layer and the ferromagnetic electrode or the ferromagnetic tunnel barrier contained in the ferromagnetic source or the ferromagnetic drain can be adjusted to parallel magnetization or antiparallel magnetization by changing the magnetization direction of the ferromagnetic electrode or the ferromagnetic tunnel barrier contained in the ferromagnetic source or the ferromagnetic drain.
[claim31]
31. The transistor as claimed in claim 1, wherein: the source is a non-magnetic source or a ferromagnetic source that comprises the tunnel barrier being a non-magnetic tunnel barrier or a ferromagnetic tunnel barrier;
and
the injection of the carriers from the source to the ferromagnetic semiconductor layer is restricted by the ferromagnetic tunnel barrier or the non-magnetic tunnel barrier in the junction of the ferromagnetic semiconductor layer with the ferromagnetic source or the non-magnetic source, while a voltage is not applied between the gate electrode and the ferromagnetic source or the non-magnetic source.
(US7397071)
The invention claimed is:
[claim32]
35. A transistor comprising: a ferromagnetic semiconductor layer;
a source that injects carriers into the ferromagnetic semiconductor layer;a drain that receives the carriers injected into the ferromagnetic semiconductor layer; and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain, wherein:at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain;
and the magnetization configuration of the ferromagnetic semiconductor layer with respect to the ferromagnetic source or the ferromagnetic drain, or to the ferromagnetic source and the ferromagnetic drain, is parallel magnetization, a threshold voltage is set as a gate voltage for generating a predetermined current between the ferromagnetic source and the ferromagnetic drain by
[claim33]
32. The transistor as claimed in claim 1, wherein: the source is a non-magnetic source or a ferromagnetic source that comprises the tunnel barrier being a non-magnetic tunnel barrier or a ferromagnetic tunnel barrier; and the carriers tunnel the ferromagnetic tunnel barrier or the non-magnetic tunnel barrier, and are injected into the ferromagnetic semiconductor layer, upon application of a voltage between the gate electrode and the ferromagnetic source or the non-magnetic source.
[claim34]
33. The transistor as claimed in claim 1, wherein: at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain;
and
the magnetization configuration of the ferromagnetic semiconductor layer with respect to the ferromagnetic source or the ferromagnetic drain, or to the ferromagnetic source and the ferromagnetic drain, is parallel magnetization, a drain current is lower than a drain current generated in a case where the magnetization configuration is antiparallel magnetization.
[claim35]
34. A transistor comprising: a ferromagnetic semiconductor layer;a source that injects carriers into the ferromagnetic semiconductor layer;a drain that receives the carriers injected into the ferromagnetic semiconductor layer;
and
a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain, wherein:at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain;
and
transconductance can be controlled in accordance with the relative magnetization direction of the ferromagnetic semiconductor layer with respect to the ferromagnetic source or the ferromagnetic drain, or to the ferromagnetic source and the ferromagnetic drain, with the same bias being applied.
[claim36]
36. A transistor comprising: a ferromagnetic semiconductor layer;a source that injects carriers into the ferromagnetic semiconductor layer;a drain that receives the carriers injected into the ferromagnetic semiconductor layer;
and
a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain, wherein:at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain;the transistor stores information in accordance with the relative magnetization direction of the ferromagnetic semiconductor layer with respect to the ferromagnetic source or the ferromagnetic drain, or to the ferromagnetic source and the ferromagnetic drain;
and
the transistor detects information stored in the transistor, based on the trans conductance of the transistor that depends on the relative magnetization direction of the ferromagnetic semiconductor layer with respect to the ferromagnetic source or the ferromagnetic drain, or to the ferromagnetic source and the ferromagnetic drain.
[claim37]
37. The transistor as claimed in claim 36, wherein the transistor rewrites information by applying such a bias to the source and the drain that the ferromagnetic semiconductor layer exhibits paramagnetism, applying a magnetic field to the ferromagnetic semiconductor layer so as to change the magnetization direction of the ferromagnetic semiconductor layer in a paramagnetic state, and then cutting off the application of the bias to the source and the drain while the application of the magnetic field is continued or applying such a bias as to return the ferromagnetic semiconductor layer to a ferromagnetic state.
[claim38]
38. The transistor as claimed in claim 36, wherein the transistor rewrites information by applying such a bias to the source and the drain as to put the ferromagnetic semiconductor layer into a ferromagnetic state with sufficiently small coercive force, applying a magnetic field to the ferromagnetic semiconductor layer so as to change magnetization direction of the ferromagnetic semiconductor layer in the ferromagnetic state with the sufficiently coercive force, and then cutting off the application of the bias to the source and the drain while the application of the magnetic field is continued or applying such a bias as to return the ferromagnetic semiconductor layer to the original ferromagnetic state with greater coercive force.
[claim39]
39. The transistor as claimed in claim 36, wherein the transistor rewrites information by applying a bias to the source and the drain so as to demagnetize the ferromagnetic semiconductor layer, and then applying a magnetic field to the ferromagnetic semiconductor layer to utilize the initial magnetization configuration.
[claim40]
40. The transistor as claimed in claim 36, wherein the transistor reads out information based on a current flowing between the drain and the gate electrode, when a predetermined voltage is applied to the drain and the gate electrode, with the source being the reference.
[claim41]
41. A memory circuit comprising: transistors, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;a ground line that collectively grounds the sources of a first group of transistors that are selected from the transistors;a word line that are collectively connected to the gates of the first group of transistors;
and
a bit line that are connected to the drains of the first group of transistors independently of one another, and are also collectively connected to a second group of transistors including transistors that do not belong to the first group.
[claim42]
42. The memory element or the memory circuit as claimed in claim 41, comprising an information rewrite unit that rewrites information stored in a transistor selected through the word line and the bit line, the rewrite being performed by applying a first voltage to the bit line and the ground line so that the ferromagnetic semiconductor layer changes from a ferromagnetic state with large coercive force to a ferromagnetic state with sufficiently small coercive force, applying a current to the word line to induce such a magnetic field as to change the magnetization direction of the ferromagnetic semiconductor layer, and then cutting off the application of the first voltage or applying a second voltage so as to return the ferromagnetic semiconductor layer to the ferromagnetic state.
[claim43]
43. The memory circuit as claimed in claim 41, wherein the memory circuit reads out information stored in a transistor selected through the word line and the bit line, based on the intensity of a current flowing between the word line and the ground line, when predetermined voltages are applied to the bit line and the word line, with the ground line being the reference.
[claim44]
44. A memory circuit comprising: transistors, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;a ground line that is collectively connected to the sources of transistor that belong to a transistor column comprising the transistors, the transistors belonging to the transistor column being aligned in one direction;a word line that is collectively connected to the gates of the transistors that belong to the transistor column;
and
bit lines that are connected to the drains of the transistors in the transistor column independently of one another.
[claim45]
45. The memory circuit as claimed in claim 44, comprising an information rewrite unit that rewrites information stored in a transistor selected through the word line and the bit line, the rewrite being performed by applying a first voltage to the bit line and the ground line so that the ferromagnetic semiconductor layer changes from a ferromagnetic state to a paramagnetic state, applying a current to the word line to induce such a magnetic field as to change the magnetization direction of the ferromagnetic semiconductor layer, and then cutting off the application of the first voltage or applying a second voltage so as to return the ferromagnetic semiconductor layer to the ferromagnetic state.
[claim46]
46. The memory circuit as claimed in claim 44, comprising an information rewrite unit that rewrites information by applying a first voltage to the bit line and the ground line so that the ferromagnetic semiconductor layer is put into to a demagnetized state, applying a current to the word line to induce such a magnetic field as to magnetize the ferromagnetic semiconductor layer, and utilizing initial magnetization characteristics after the application of the first voltage is cut off.
[claim47]
47. A memory circuit comprising: transistors, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;a ground line that collectively grounds the sources of a first group of transistors that are selected from the transistors;a bit line that are collectively connected to the drains of the first group of transistors;
and
a word line that are connected to the gates of the first group of transistors independently of one another, and are also collectively connected to a second group of transistors including transistors that do not belong to the first group.
[claim48]
48. The memory circuit as claimed in claim 47, comprising an information rewrite unit that collectively rewrites information stored in the transistors that are connected to the bit line and the ground line and are also connected to the word lines to which a current is applied, the rewrite being performed by applying a first voltage to the bit line and the ground line so that the ferromagnetic semiconductor layer changes from a ferromagnetic state with large coercive force to a paramagnetic state, applying the current simultaneously to the word lines to induce such a magnetic field as to change the magnetization direction of the ferromagnetic semiconductor layer, and then cutting off the application of the first voltage or applying a second voltage so as to return the ferromagnetic semiconductor layer to the ferromagnetic state.
[claim49]
49. The memory circuit as claimed in claim 47, comprising an information rewrite unit that collectively rewrites information stored in the transistors that are connected to the bit line and the ground line and are also connected to the word lines to which a current is applied, the rewrite being performed by applying a first voltage to the bit line and the ground line so that the ferromagnetic semiconductor layer changes from a ferromagnetic state with large coercive force to a ferromagnetic state with sufficiently small coercive force, applying the current simultaneously to the word lines to induce such a magnetic field as to change the magnetization direction of the ferromagnetic semiconductor layer, and then cutting off the application of the first voltage or applying a second voltage so as to return the ferromagnetic semiconductor layer to the ferromagnetic state.
[claim50]
50. The memory circuit as claimed in claim 47, comprising an information rewrite unit that rewrites information by applying a first voltage to the bit line and the ground line so that the ferromagnetic semiconductor layer is put into to a demagnetized state, and applying a current to the word lines to induce such a magnetic field as to magnetize the ferromagnetic semiconductor layer utilizing initial magnetization characteristics after the application of the first voltage is cut off.
[claim51]
51. The memory circuit as claimed in claim 47, wherein the memory circuit reads out information stored in a transistor selected through the word line and the bit line, based on the size of a current flowing between the word line and the ground line, when predetermined voltages are applied to the bit line and the word line, with the ground line being the reference.
[claim52]
52. A memory circuit comprising: transistors being arranged in a matrix fashion, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;ground lines that are collectively connected to the sources of the transistors aligned in a column direction;word lines that are collectively connected to the gate electrodes of the transistors aligned in the column direction;
and
bit lines that are collectively connected to the drains of the transistors aligned in a row direction.
[claim53]
53. A memory circuit comprising: a first transistor and a second transistor being adjacent to each other, each of the first and the second transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;a word line that is respectively connected to the gate electrode of the first transistor and the gate electrode of the second transistor;a first bit line that is connected to the drain of the first transistor;a second bit line that is connected to the drain of the second transistor;a source that is shared between the first and second transistors;
and
a line that grounds the shared source, and extends in a direction perpendicular to the bit lines.
[claim54]
54. A memory circuit comprising: transistors, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;a ground line that is collectively connected to the sources of transistor that belong to a transistor row comprising the transistors, the transistors belonging to the transistor row being aligned in one direction;a bit line that is collectively connected to the drains of the transistors that belong to the transistor row;
and
word lines that are connected to the gates of the transistors in the transistor row independently of one another.
[claim55]
55. A memory circuit comprisi(...)
  • 発明者/出願人(英語)
  • SUGAHARA SATOSHI
  • TANAKA MASAAKI
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
国際特許分類(IPC)
米国特許分類/主・副
  • 257/213
  • 257/197
  • 257/E21.665
  • 257/E27.005
参考情報 (研究プロジェクト等) PRESTO Nanostructure and Material Property AREA
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