TOP > 外国特許検索 > Reconfigurable logic circuit using a transistor having spin-dependent transfer characteristics

Reconfigurable logic circuit using a transistor having spin-dependent transfer characteristics

外国特許コード F110005384
整理番号 K02010US
掲載日 2011年9月5日
出願国 アメリカ合衆国
出願番号 55065204
公報番号 20060114018
公報番号 7545013
出願日 平成16年3月26日(2004.3.26)
公報発行日 平成18年6月1日(2006.6.1)
公報発行日 平成21年6月9日(2009.6.9)
国際出願番号 JP2004004379
国際公開番号 WO2004086625
国際出願日 平成16年3月26日(2004.3.26)
国際公開日 平成16年10月7日(2004.10.7)
優先権データ
  • 特願2003-086499 (2003.3.26) JP
  • 2004WO-JP04379 (2004.3.26) WO
発明の名称 (英語) Reconfigurable logic circuit using a transistor having spin-dependent transfer characteristics
発明の概要(英語) (US7545013)
A nonvolatilely reconfigurable logical circuit is built.
It is a reconfigurable logical circuit based on the CMOS configuration using the spin MOSFET.
By changing the transmission characteristic of each transistor in accordance with the magnetization states of Tr1, Tr2, Tr5, and Tr8 which are spin MOSFETs, it is possible to reconfigure all the two-input symmetric functions AND/OR/XOR/NAND/NOR/XNOR/"1"/"0".
Since it is possible to constitute the logical function by a small number of non-volatile elements, it is possible to reduce the chip area, thereby increasing the speed and reducing the power consumption.
特許請求の範囲(英語) [claim1]
1. A circuit comprising: a first terminal that outputs an operating point;
a first circuit group charging the first terminal;a second circuit group discharging the first terminal;an applying portion applying a weighted mean of a plurality of inputs to one or both of the first circuit group and the second group;a spin transistor having transfer characteristics depending on the spin direction of conduction carriers and being included in one or both of the first circuit group and the second circuit group;
and
an output terminal that outputs a Boolean function of a plurality of inputs based on the operating point, whereinthe operating point is changed based on the transfer characteristics, thereby reconfiguring the Boolean function.
[claim2]
2. The circuit as claimed in claim 1, wherein: the spin transistor includes at least two ferromagnetic layers, and has the transfer characteristics depending on magnetization states of the ferromagnetic layers;
and
the magnetization states of the spin transistor is changed to move the operating point, thereby reconfiguring the Boolean function.
[claim3]
3. The circuit as claimed in claim 2, wherein: the spin transistor has at least one ferromagnetic body ("free layer") with a magnetization direction that can be controlled independently, and at least one ferromagnetic body ("pin layer") with a fixed magnetization direction;
and
the spin transistor changes the operating point based on two of the magnetization states including a first state in which the free layer and the pin layer have the same magnetization directions ("parallel magnetization"), and a second state in which the free layer and the pin layer have the opposite magnetizing states to each other ("antiparallel magnetization").
[claim4]
4. The circuit as claimed in claim 1, wherein the first terminal has a potential that is determined by changing the spin directions of the condition carriers of the spin transistor or by controlling the transfer characteristics depending on magnetization state of the spin transistor.
[claim5]
5. The circuit as claimed in claim 1, wherein the applying portion has a neuron MOS (nu MOS) structure including capacitors weighing the plurality of inputs with capacitance thereof and a floating gate connecting weighted input signals.
[claim6]
6. The circuit as claimed in claim 5, wherein the weighted input signals are weighted so as to be substantially equal to one another.
[claim7]
7. The circuit as claimed in claim 1, wherein a logic threshold value for dividing a potential generated in the first terminal into an output of a logic level "0" and an output of a logic level "1" is set with respect to the operating point that varies according to a variation in the transfer characteristics of the spin transistor.
[claim8]
8. The circuit as claimed in claim 1, wherein an A-D converter with a predetermined logic threshold value is connected to an output terminal of the circuit.
[claim9]
9. The circuit as claimed in claim 1, wherein the spin transistor is a MOSFET-type spin transistor ("spin MOSFET") that are formed with a source and a drain, including a MOS structure and a ferromagnetic body.
[claim10]
10. The circuit as claimed in claim 1, wherein the first circuit group includes a MOSFET of a first conductivity type or a spin MOSFET of the first conductivity type, and the second circuit group includes a MOSFET of the same conductivity type as the first conductivity type or a spin MOSFET of the same conductivity type as the first conductivity type.
[claim11]
11. The circuit as claimed in claim 10, wherein the first and second circuit groups or one of the first and second circuit groups comprises a circuit that controls a potential of the first terminal by connecting a source or a drain of another spin MOSFET to the first terminal, and connecting a level shift circuit to a gate of the another spin MOSFET, the level shift circuit turning on the another spin MOSFET only when a predetermined input is made.
[claim12]
12. The circuit as claimed in claim 11, wherein the level shift circuit is formed with an E/E, E/D, or CMOS inverter.
[claim13]
13. The circuit as claimed in claim 11, wherein the circuit is a reconfigurable logic circuit that includes an A-D converter having the first terminal as an input.
[claim14]
14. The circuit as claimed in claim 11, wherein the circuit is a reconfigurable logic circuit that includes an inverter having an output of an A-D converter as an input, and can achieve all symmetric Boolean functions.
[claim15]
15. The circuit as claimed in claim 10, wherein the second circuit group comprises a circuit that controls a potential of the first terminal by connecting a drain of another spin MOSFET of n-channel type to the first terminal, and connecting a level shift circuit to a gate of the another spin MOSFET of n-channel type, the another spin MOSFET of n-channel having a source grounded, the level shift circuit turning on the another spin MOSFET of n-channel type only when an input is A=B="0".
[claim16]
16. The circuit as claimed in claim 10, wherein the first circuit group comprises a circuit that controls a potential of the first terminal by connecting a drain of another spin MOSFET of p-channel type to the first terminal, and connecting a level shift circuit to a gate of the another spin MOSFET of p-channel type, the another spin MOSFET of p-channel having a source connected to a supply voltage, the level shift circuit turning on the another spin MOSFET of p-channel type only when an input is A=B="1".
[claim17]
17. The circuit as claimed in claim 1, comprising an E/E circuit that includes a structure in which a source of an enhancement MOSFET or an enhancement spin MOSFET contained in the first circuit group is connected to a drain of an enhancement MOSFET or an enhancement spin MOSFET contained in the second circuit group, and a first terminal that is formed at the connection portion.
[claim18]
18. The circuit as claimed in claim 17, wherein the drain of the enhancement MOSFET or the enhancement spin MOSFET contained in the first circuit group in the E/E circuit is connected to a gate of the enhancement MOSFET or the enhancement spin MOSFET.
[claim19]
19. The circuit as claimed in claim 17, wherein the enhancement MOSFET or the enhancement spin MOSFET contained in the second circuit group in the E/E circuit has a nu MOS structure.
[claim20]
20. The circuit as claimed in claim 19, wherein the nu MOS structure has two inputs (A and B) weighted with capacitances by capacitors.
[claim21]
21. The circuit as claimed in claim 1, comprising an E/D circuit that includes a structure in which a source of a depletion MOSFET or a depletion spin MOSFET contained in the first circuit group is connected to a drain of an enhancement MOSFET or an enhancement spin MOSFET contained in the second circuit group, and a first terminal that is formed at the connection portion.
[claim22]
22. The circuit as claimed in claim 21, wherein the source of the depletion MOSFET or the depletion spin MOSFET contained in the first circuit group in the E/D circuit is connected to a gate of the depletion MOSFET or the depletion spin MOSFET.
[claim23]
23. The circuit as claimed in claim 21, wherein the enhancement MOSFET or the enhancement spin MOSFET contained in the second circuit group in the E/D circuit has a nu MOS structure.
[claim24]
24. The circuit as claimed in claim 1, wherein the circuit is a NAND/NOR reconfigurable logic circuit or an AND/OR reconfigurable logic circuit that includes a A-D converter having the first terminal as an input.
[claim25]
25. The circuit as claimed in claim 1, wherein the first circuit group includes a MOSFET of a first conductivity type or a spin MOSFET of the first conductivity type, and the second circuit group includes a MOSFET of a second conductivity type different from the first conductivity type or a spin MOSFET of the second conductivity type.
[claim26]
26. The circuit as claimed in claim 25, comprising a CMOS circuit that includes a structure in which a p-channel MOSFET or a p-channel spin MOSFET contained in the first circuit group is connected to an n-channel MOSFET or an n-channel spin MOSFET contained in the second circuit group with a shared drain terminal, and a first terminal that is formed at the shared drain terminal.
[claim27]
27. The circuit as claimed in claim 25, comprising a CMOS circuit that is formed with a p-channel spin MOSFET contained in the first circuit group and an n-channel spin MOSFET contained in the second circuit group.
[claim28]
28. The circuit as claimed in claim 25, wherein the p-channel MOSFET or the p-channel spin MOSFET, and the n-channel MOSFET or the n-channel spin MOSFET of the CMOS circuit have a shared floating gate forming a nu MOS structure.
[claim29]
29. The circuit as claimed in claim 28, wherein the nu MOS structure has two inputs (A and B) weighted with capacitances by capacitors.
[claim30]
30. The circuit as claimed in claim 25, wherein the circuit is an AND/OR reconfigurable logic circuit or a NAND/NOR reconfigurable logic circuit that includes an A-D converter having the first terminal as an input.
[claim31]
31. The circuit as claimed in claim 25, wherein the first and second circuit groups, or one of the first and second circuit groups comprises a circuit that controls a potential of the first terminal by connecting a source or a drain of another spin MOSFET to the first terminal, and connecting a level shift circuit to a gate of the another spin MOSFET, the level shift circuit turning on the another spin MOSFET only when a predetermined input is made.
[claim32]
32. The circuit as claimed in claim 31, wherein the level shift circuit is formed with an E/E, E/D, or CMOS inverter.
[claim33]
33. The circuit as claimed in claim 25, wherein the second circuit group comprises a circuit that controls a potential of the first terminal by connecting a drain of another spin MOSFET of n-channel type to the first terminal, and connecting a level shift circuit to a gate of the another spin MOSFET of n-channel type, the another spin MOSFET of n-channel having a source grounded, the level shift circuit turning on the another spin MOSFET of n-channel type only when an input is A=B="0".
[claim34]
34. The circuit as claimed in claim 25, wherein the circuit is an AND/OR/XNOR reconfigurable logic circuit or a NAND/NOR/XOR reconfigurable logic circuit that includes an A-D converter having the first terminal as an input.
[claim35]
35. The circuit as claimed in claim 25, wherein the first circuit group comprises a circuit that controls the potential of the first terminal by connecting the drain of the another spin MOSFET of p-channel type to the first terminal, and connecting a level shift circuit to the gate of the another spin MOSFET of p-channel type, the another spin MOSFET of p-channel having the source connected to a supply voltage, the level shift circuit turning on the another spin MOSFET of p-channel type only when an input is A=B="1".
[claim36]
36. The circuit as claimed in claim 25, wherein the circuit is an AND/OR/XOR reconfigurable logic circuit or a NAND/NOR/XNOR reconfigurable logic circuit that includes an A-D converter having the first terminal as an input.
[claim37]
37. The circuit as claimed in claim 25, wherein the circuit is a reconfigurable logic circuit that includes an inverter having an output of an A-D converter as an input, and can achieve all symmetric Boolean functions.
[claim38]
38. The circuit as claimed in claim 25, wherein the circuit is formed with a circuit group that is characterized by: controlling a potential of the first terminal by connecting a drain of another spin MOSFET of n-channel type to the first terminal, and connecting a level shift circuit to a gate of the another spin MOSFET of n-channel type, the another spin MOSFET of n-channel having a source grounded, the level shift circuit turning on the another spin MOSFET of n-channel type only when an input is A=B="1";
and
controlling the potential of the first terminal by connecting a drain of another spin MOSFET of p-channel type to the first terminal, and connecting a level shift circuit to a gate of the another spin MOSFET of p-channel type, the another spin MOSFET of p-channel having a source connected to a supply voltage, the level shift circuit turning on the another spin MOSFET of p-channel type only when an input is A=B="0".
[claim39]
39. The circuit as claimed in claim 38, wherein the circuit is an all symmetric Boolean function logic circuit that includes an A-D converter having the first terminal as an input.
[claim40]
40. An integrated circuit comprising the circuit including: a first terminal that outputs an operating point;
a first circuit group charging the first terminala second circuit group discharging the first terminal;an applying portion applying a weighted mean of a plurality of inputs to one or both of the first circuit group and the second circuit group;a spin transistor having transfer characteristics depending on the spin direction of conduction carriers and being included in one or both of the first circuit group and the second circuit group;
and
an output terminal that outputs a Boolean function of a plurality of inputs based on the operating point, whereinthe operating point is changeable based on the transfer characteristics thereby reconfiguring the Boolean function.
  • 発明者/出願人(英語)
  • SUGAHARA SATOSHI
  • MATSUNO TOMOHIRO
  • TANAKA MASAAKI
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
国際特許分類(IPC)
米国特許分類/主・副
  • 257/421
  • 257/295
  • 257/422
  • 257/425
  • 257/E29.164
  • 257/E29.323
参考情報 (研究プロジェクト等) PRESTO Nanostructure and Material Property AREA
ライセンスをご希望の方、特許の内容に興味を持たれた方は、問合せボタンを押してください。

PAGE TOP

close
close
close
close
close
close