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Signal reproducing device

外国特許コード F110005409
整理番号 K03101WO
掲載日 2011年9月5日
出願国 アメリカ合衆国
出願番号 92009108
公報番号 20110050332
公報番号 8314646
出願日 平成20年9月2日(2008.9.2)
公報発行日 平成23年3月3日(2011.3.3)
公報発行日 平成24年11月20日(2012.11.20)
国際出願番号 JP2008065758
国際公開番号 WO2009107263
国際出願日 平成20年9月2日(2008.9.2)
国際公開日 平成21年9月3日(2009.9.3)
優先権データ
  • 特願2008-050389 (2008.2.29) JP
  • 2008JP065758 (2008.9.2) WO
発明の名称 (英語) Signal reproducing device
発明の概要(英語) The purpose is to detect minute electrical signals embedded in noise with a simple device configuration and easily reduce the area of the device by utilizing a semiconductor device in particular.
This signal reproducing device (1) includes: N FETs (61 to 6N) each receiving a common input signal (VIN) at a gate terminal and having a bias voltage (VDD) applied to a drain terminal; and an adder circuit (4) connected to source terminals of the FETs (61 to 6N), for combining currents between the drain terminals and the source terminals of the FETs (61 to 6N) and outputting the resulting current, wherein the FETs (61 to 6N) and the bias voltage (VDD) are set so that a voltage at the gate terminal having the common input signal (VIN) applied thereto falls within a subthreshold region of voltages less than a threshold voltage of the FETs (61 to 6N).
従来技術、競合技術の概要(英語) BACKGROUND ART
Conventionally, for detecting minute electrical signals having noise added, a method of filtering out frequency components containing noise components, a method of averaging input signals to attenuate noise and other methods have been employed.
As disclosed in patent document 1, also a method of repeating data processing such as power spectrum analysis and statistical analysis to detect minute signals embedded in noise has been devised.

CITATION LIST

Patent Literature
Patent document 1: Japanese Unexamined Patent Application Publication No. 2002-221546

特許請求の範囲(英語) [claim1]
1. A signal reproducing device comprising: a plurality of semiconductor field-effect transistors each receiving a common input signal at a gate terminal and having a bias voltage applied to a drain terminal;
an adder circuit connected to source terminals of the plurality of semiconductor field-effect transistors for adding currents between the drain terminals and the source terminals of the plurality of semiconductor field-effect transistors and outputting the resulting current; and
a noise source connected to at least one of the drain terminal and the source terminal for adding noise to the bias voltage,
wherein the plurality of semiconductor field-effect transistors and the bias voltage are set so that a voltage at the gate terminal having the common input signal applied thereto falls within a subthreshold region of voltages less than a threshold voltage of the plurality of semiconductor field-effect transistors.
[claim2]
2. The signal reproducing device of claim 1 further comprising: a noise source connected to the gate terminal for adding noise to the input signal.
[claim3]
3. The signal reproducing device of claim 1 further comprising: a voltage source circuit that adds an offset to the input signal so that the voltage at the gate terminal falls within the subthreshold region.
  • 発明者/出願人(英語)
  • KASAI SEIYA
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
国際特許分類(IPC)
米国特許分類/主・副
  • 327/361
  • 327/408
参考情報 (研究プロジェクト等) PRESTO Materials and processes for innovative next-generation devices AREA
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