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FIELD EFFECT TRANSISTOR AND MEMORY DEVICE

外国特許コード F110005917
整理番号 E08610WO
掲載日 2011年11月16日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2011JP060521
国際公開番号 WO 2011/138941
国際出願日 平成23年5月2日(2011.5.2)
国際公開日 平成23年11月10日(2011.11.10)
優先権データ
  • 特願2010-107772 (2010.5.7) JP
  • 特願2010-107773 (2010.5.7) JP
  • 特願2010-107775 (2010.5.7) JP
  • 特願2010-203785 (2010.9.10) JP
  • 特願2010-203788 (2010.9.10) JP
  • 特願2010-203791 (2010.9.10) JP
発明の名称 (英語) FIELD EFFECT TRANSISTOR AND MEMORY DEVICE
発明の概要(英語) Disclosed is a field effect transistor, comprising a channel layer, a gate electrode layer, and a gate insulator layer. The gate insulator layer is made from a ferroelectric layer, and is divided into two regions: a first region for information storage, having a prescribed first coercive voltage (Vc1), and a second region for information read/write, having a layer with a different thickness from the first region. An on voltage (Von) and an off voltage (Voff) for controlling the information and read/write, and the first coercive voltage (Vc1), satisfy the relation -Vc1 < Voff < Von < Vc1. A single field effect transistor has the information storage function and the information read/write function therein. When the disclosed field effect transistor is employed as a memory cell in a NAND memory device, the problems of read disturb and write disturb do not arise. Additionally, the disclosed field effect transistor is effective with respect to achieving large-scale integration.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • MIYASAKO, Takaaki
  • TOKUMITSU, Eisuke
  • SHIMODA, Tatsuya
国際特許分類(IPC)
指定国 AE(UTILITY MODEL),AG,AL(UTILITY MODEL),AM(PROVISIONAL PATENT)(UTILITY MODEL),AO(UTILITY MODEL),AT(UTILITY MODEL),AU,AZ(UTILITY MODEL),BA,BB,BG(UTILITY MODEL),BH(UTILITY MODEL),BR(UTILITY MODEL),BW,BY(UTILITY MODEL),BZ(UTILITY MODEL),CA,CH,CL(UTILITY MODEL),CN(UTILITY MODEL),CO(UTILITY MODEL),CR(UTILITY MODEL),CU(INVENTOR'S CERTIFICATE),CZ(UTILITY MODEL),DE(UTILITY MODEL),DK(UTILITY MODEL),DM,DO(UTILITY MODEL),DZ,EC(UTILITY MODEL),EE(UTILITY MODEL),EG(UTILITY MODEL),ES(UTILITY MODEL),FI(UTILITY MODEL),GB,GD,GE(UTILITY MODEL),GH(UTILITY CERTIFICATE),GM,GT(UTILITY MODEL),HN(UTILITY MODEL),HR(CONSENSUAL PATENT),HU(UTILITY MODEL),ID,IL,IN,IS,JP(UTILITY MODEL),KE(UTILITY MODEL),KG(UTILITY MODEL),KM,KN,KP(INVENTOR'S CERTIFICATE)(UTILITY MODEL),KR(UTILITY MODEL),KZ(PROVISIONAL PATENT)(UTILITY MODEL),LA,LC,LK,LR,LS(UTILITY MODEL),LT,LU,LY,MA,MD(UTILITY MODEL),ME,MG,MK,MN,MW,MX(UTILITY MODEL),MY(UTILITY-INNOVATION),MZ(UTILITY MODEL),NA,NG,NI(UTILITY MODEL),NO,NZ,OM(UTILITY MODEL),PE(UTILITY MODEL),PG,PH(UTILITY MODEL),PL(UTILITY MODEL),PT(UTILITY MODEL),RO,RS(PETTY PATENT),RU(UTILITY MODEL),SC,SD,SE,SG,SK(UTILITY MODEL),SL(UTILITY MODEL),SM,ST,SV(UTILITY MODEL),SY,TH(PETTY PATENT),TJ(UTILITY MODEL),TM(PROVISIONAL PATENT),TN,TR(UTILITY MODEL),TT(UTILITY CERTIFICATE),TZ,UA(UTILITY MODEL),UG(UTILITY CERTIFICATE),US,UZ(UTILITY MODEL),VC(UTILITY CERTIFICATE),VN(PATENT FOR UTILITY SOLUTION),ZA,ZM,ZW,EP(AL,AT,BE,BG,CH,CY,CZ,DE,DK,EE,ES,FI,FR,GB,GR,HR,HU,IE,IS,IT,LT,LU,LV,MC,MK,MT,NL,NO,PL,PT,RO,RS,SE,SI,SK,SM,TR),OA(BF(UTILITY MODEL),BJ(UTILITY MODEL),CF(UTILITY MODEL),CG(UTILITY MODEL),CI(UTILITY MODEL),CM(UTILITY MODEL),GA(UTILITY MODEL),GN(UTILITY MODEL),GQ(UTILITY MODEL),GW(UTILITY MODEL),ML(UTILITY MODEL),MR(UTILITY MODEL),NE(UTILITY MODEL),SN(UTILITY MODEL),TD(UTILITY MODEL),TG(UTILITY MODEL)),AP(BW(UTILITY MODEL),GH(UTILITY MODEL),GM(UTILITY MODEL),KE(UTILITY MODEL),LR(UTILITY MODEL),LS(UTILITY MODEL),MW(UTILITY MODEL),MZ(UTILITY MODEL),NA(UTILITY MODEL),SD(UTILITY MODEL),SL(UTILITY MODEL),SZ(UTILITY MODEL),TZ(UTILITY MODEL),UG(UTILITY MODEL),ZM(UTILITY MODEL),ZW(UTILITY MODEL)),EA(AM,AZ,BY,KG,KZ,MD,RU,TJ,TM)
参考情報 (研究プロジェクト等) ERATO SHIMODA Nano-Liquid Process AREA
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