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METHOD AND PROGRAM FOR GENERATING TEST PATTERN FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER-READABLE STORAGE MEDIUM 新技術説明会

外国特許コード F120006210
整理番号 S2010-0242-N0
掲載日 2012年2月9日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2011JP000059
国際公開番号 WO 2011/086884
国際出願日 平成23年1月7日(2011.1.7)
国際公開日 平成23年7月21日(2011.7.21)
優先権データ
  • 特願2010-007003 (2010.1.15) JP
発明の名称 (英語) METHOD AND PROGRAM FOR GENERATING TEST PATTERN FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER-READABLE STORAGE MEDIUM 新技術説明会
発明の概要(英語) Provided is a method for generating a test pattern such that the temperature of a semiconductor integrated circuit during testing is spaciously homogenized. The method comprises the steps of sequentially selecting a test pattern from an original test pattern series of multiple test patterns including don't cares, setting a don't care value to the selected test pattern for each almost equally divided layout region of the semiconductor integrated circuit to estimate power consumption when the test pattern in question is applied to the semiconductor integrated circuit, repetitively changing the don't care value and estimating power consumption of each layout region for the selected layout region to find a don't care value such that the variation in the power consumption of each layout region becomes extremely low, determining the found don't care value as a don't care value for the selected test pattern, and generating a first new test pattern series of multiple test patterns including no don't cares.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
  • Kyushu Institute of Technology
  • 発明者(英語)
  • INOUE, Michiko
  • YONEDA, Tomokazu
  • SATO, Yasuo
国際特許分類(IPC)
指定国 AE(UTILITY MODEL),AG,AL(UTILITY MODEL),AM(PROVISIONAL PATENT)(UTILITY MODEL),AO(UTILITY MODEL),AT(UTILITY MODEL),AU,AZ(UTILITY MODEL),BA,BB,BG(UTILITY MODEL),BH(UTILITY MODEL),BR(UTILITY MODEL),BW,BY(UTILITY MODEL),BZ(UTILITY MODEL),CA,CH,CL(UTILITY MODEL),CN(UTILITY MODEL),CO(UTILITY MODEL),CR(UTILITY MODEL),CU(INVENTOR'S CERTIFICATE),CZ(UTILITY MODEL),DE(UTILITY MODEL),DK(UTILITY MODEL),DM,DO(UTILITY MODEL),DZ,EC(UTILITY MODEL),EE(UTILITY MODEL),EG(UTILITY MODEL),ES(UTILITY MODEL),FI(UTILITY MODEL),GB,GD,GE(UTILITY MODEL),GH(UTILITY CERTIFICATE),GM,GT(UTILITY MODEL),HN(UTILITY MODEL),HR(CONSENSUAL PATENT),HU(UTILITY MODEL),ID,IL,IN,IS,JP(UTILITY MODEL),KE(UTILITY MODEL),KG(UTILITY MODEL),KM,KN,KP(INVENTOR'S CERTIFICATE)(UTILITY MODEL),KR(UTILITY MODEL),KZ(PROVISIONAL PATENT)(UTILITY MODEL),LA,LC,LK,LR,LS(UTILITY MODEL),LT,LU,LY,MA,MD(UTILITY MODEL),ME,MG,MK,MN,MW,MX(UTILITY MODEL),MY(UTILITY-INNOVATION),MZ(UTILITY MODEL),NA,NG,NI(UTILITY MODEL),NO,NZ,OM(UTILITY MODEL),PE(UTILITY MODEL),PG,PH(UTILITY MODEL),PL(UTILITY MODEL),PT(UTILITY MODEL),RO,RS(PETTY PATENT),RU(UTILITY MODEL),SC,SD,SE,SG,SK(UTILITY MODEL),SL(UTILITY MODEL),SM,ST,SV(UTILITY MODEL),SY,TH(PETTY PATENT),TJ(UTILITY MODEL),TM(PROVISIONAL PATENT),TN,TR(UTILITY MODEL),TT(UTILITY CERTIFICATE),TZ,UA(UTILITY MODEL),UG(UTILITY CERTIFICATE),US,UZ(UTILITY MODEL),VC(UTILITY CERTIFICATE),VN(PATENT FOR UTILITY SOLUTION),ZA,ZM,ZW,EP(AL,AT,BE,BG,CH,CY,CZ,DE,DK,EE,ES,FI,FR,GB,GR,HR,HU,IE,IS,IT,LT,LU,LV,MC,MK,MT,NL,NO,PL,PT,RO,RS,SE,SI,SK,SM,TR),OA(BF(UTILITY MODEL),BJ(UTILITY MODEL),CF(UTILITY MODEL),CG(UTILITY MODEL),CI(UTILITY MODEL),CM(UTILITY MODEL),GA(UTILITY MODEL),GN(UTILITY MODEL),GQ(UTILITY MODEL),GW(UTILITY MODEL),ML(UTILITY MODEL),MR(UTILITY MODEL),NE(UTILITY MODEL),SN(UTILITY MODEL),TD(UTILITY MODEL),TG(UTILITY MODEL)),AP(BW(UTILITY MODEL),GH(UTILITY MODEL),GM(UTILITY MODEL),KE(UTILITY MODEL),LR(UTILITY MODEL),LS(UTILITY MODEL),MW(UTILITY MODEL),MZ(UTILITY MODEL),NA(UTILITY MODEL),SD(UTILITY MODEL),SL(UTILITY MODEL),SZ(UTILITY MODEL),TZ(UTILITY MODEL),UG(UTILITY MODEL),ZM(UTILITY MODEL),ZW(UTILITY MODEL)),EA(AM,AZ,BY,KG,KZ,MD,RU,TJ,TM)
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