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Memory cell block, manufacturing method therefor, memory device, and method for driving a memory device

外国特許コード F120007052
整理番号 E086P16TW
掲載日 2012年11月22日
出願国 台湾
出願番号 100132261
公報番号 201222827
出願日 平成23年9月7日(2011.9.7)
公報発行日 平成24年6月1日(2012.6.1)
優先権データ
  • 特願2010-203783 (2010.9.10) JP
発明の名称 (英語) Memory cell block, manufacturing method therefor, memory device, and method for driving a memory device
発明の概要(英語)

This memory cell block is provided with a plurality of memory cells connected in series, each memory cell comprising a solid-state electronic element in which the following are connected in parallel: an information-storage transistor (TR1) that has a first gate-insulating layer comprising a ferroelectric layer

and an information-reading/writing transistor (TR2) that has a second gate-insulating layer. First channel regions and second channel regions comprise conductor layers or semiconductor layers formed in the same step. Each two adjacent memory cells are connected by a connection layer contiguous with the first channel regions and the second channel regions. When this memory cell block is used as a NAND memory device, the "write disturb problem" and "read disturb problem" are eliminated. Also, it is possible to form the first channel regions, the second channel regions, and the connection layers in one step. Furthermore, it is possible to reduce the contact resistance between the first and second channel regions and the connection layers.

  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • SHIMODA, TATSUYA,
  • TOKUMITSU, EISUKE,
  • MIYASAKO, TAKAAKI,
  • BUI, NGUYEN QUOC TRINH
国際特許分類(IPC)
参考情報 (研究プロジェクト等) ERATO SHIMODA Nano-Liquid Process AREA
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