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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 新技術説明会 実績あり

外国特許コード F130007179
掲載日 2013年3月5日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2011JP055546
国際公開番号 WO 2011/111754
国際出願日 平成23年3月9日(2011.3.9)
国際公開日 平成23年9月15日(2011.9.15)
優先権データ
  • 特願2010-052173 (2010.3.9) JP
発明の名称 (英語) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 新技術説明会 実績あり
発明の概要(英語)

Disclosed is a semiconductor device in which a diode and a transistor coexist on the same substrate, and in which leakage current that is generated unrelated to control performed by a gate electrode of the transistor is suppressed, and also provided is a method for manufacturing the semiconductor device. A P-type well diffusion layer and a P-type extraction electrode region are formed in an N-type semiconductor layer, which is formed by a high resistance N-type substrate, and are fixed to ground potential by an electrode. The potential near the surface of the P-type well diffusion layer is held at the ground potential because a depletion layer that spreads toward the P-type well diffusion layer does not reach the boundary surface with an embedded oxide film. When a voltage is applied from a power supply voltage to the rear surface of the N-type semiconductor layer and a cathode electrode, the generation of leakage current unrelated to the control performed by the gate electrode can be suppressed because a channel region on the embedded oxide film side of a MOS-type transistor formed in the P-type semiconductor layer does not act.

  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION,
  • OKI SEMICONDUCTOR CO., LTD,
  • ARAI, YASUO,
  • OKIHARA, MASAO,
  • KASAI, HIROKI
  • 発明者(英語)
  • ARAI, YASUO,
  • OKIHARA, MASAO,
  • KASAI, HIROKI
国際特許分類(IPC)
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