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CLOCK DATA RECOVERY CIRCUIT AND WIRELESS MODULE INCLUDING SAME

外国特許コード F130007205
整理番号 S2012-1009-N0
掲載日 2013年3月7日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2011JP053416
国際公開番号 WO 2012/111133
国際出願日 平成23年2月17日(2011.2.17)
国際公開日 平成24年8月23日(2012.8.23)
発明の名称 (英語) CLOCK DATA RECOVERY CIRCUIT AND WIRELESS MODULE INCLUDING SAME
発明の概要(英語)

This clock data recovery circuit (11) is provided with: a ring oscillator (17)

an oscillation control circuit unit (15) which starts and stops operation of the ring oscillator (17) depending upon the presence or absence of input of a PWM signal

a counter circuit unit (19) for counting pulse signals and holding an N-bit count value

a register circuit unit (21) which has an M-bit register and is configured so as to be able to transfer the upper M bits among the N-bit count value as a reference count value in response to the input of a transfer signal

a comparator circuit unit (25) which outputs a timing clock if the count number held by the counter circuit unit (19) exceeds the reference count value held by the register circuit unit (21)

and a transfer control circuit unit (23) which, in synchronization with the start-up timing of the PWM signal, generates the transfer signal for transferring the reference count value from the counter circuit unit (19) to the register circuit unit (21) and a reset signal for resetting the counter circuit unit (19).

  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY,
  • SANO EIICHI,
  • AMEMIYA YOSHIHITO
  • 発明者(英語)
  • SANO EIICHI,
  • AMEMIYA YOSHIHITO
国際特許分類(IPC)
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