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TEST PATTERN MANUFACTURING DEVICE, FAULT DETECTION SYSTEM, TEST PATTERN MANUFACTURING METHOD, PROGRAM, AND RECORDING MEDIUM

外国特許コード F130007589
整理番号 S2012-0301-N0
掲載日 2013年7月31日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2013JP050150
国際公開番号 WO 2013/105564
国際出願日 平成25年1月9日(2013.1.9)
国際公開日 平成25年7月18日(2013.7.18)
優先権データ
  • 特願2012-002214 (2012.1.10) JP
発明の名称 (英語) TEST PATTERN MANUFACTURING DEVICE, FAULT DETECTION SYSTEM, TEST PATTERN MANUFACTURING METHOD, PROGRAM, AND RECORDING MEDIUM
発明の概要(英語)

Provided are a test pattern manufacturing device, etc., with which, while effecting characteristic maintenance of an original test pattern, it is possible to manufacture a new test pattern. This test pattern manufacturing device, which manufactures a test pattern which is inputted into a test object circuit of a scan test, comprises logic value generation means for generating a new logic value by referring to the logic values of a supplied first bit, second bit, and third bit, and either maintaining or inverting the logic value of the second bit. The logic value of the first bit is either that which an initial test pattern which is a supplied test pattern has, or that which a new test pattern which the test pattern manufacturing device has manufactured on the basis of the initial test pattern has. The logic value of the second bit is that which the initial test pattern has. The logic value of the third bit is either that which the initial test pattern has, or that which the new test pattern has.

  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • KYUSHU INSTITUTE OF TECHNOLOGY
  • 発明者(英語)
  • SATO YASUO,
  • KAJIHARA SEIJI
国際特許分類(IPC)
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