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INTEGRAL A/D CONVERTER AND CMOS IMAGE SENSOR 新技術説明会

外国特許コード F130007680
整理番号 S2012-0418-N0
掲載日 2013年10月17日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2013JP053734
国際公開番号 WO 2013/122221
国際出願日 平成25年2月15日(2013.2.15)
国際公開日 平成25年8月22日(2013.8.22)
優先権データ
  • 特願2012-033196 (2012.2.17) JP
発明の名称 (英語) INTEGRAL A/D CONVERTER AND CMOS IMAGE SENSOR 新技術説明会
発明の概要(英語)

Provided is an integral A/D converter in which power consumption can be kept down while the conversion accuracy and conversion speed are improved. This integral A/D conversion circuit (1) is provided with: a comparator (10) for comparing the input voltage and the reference voltage of a ramp waveform, and outputting a comparison signal

a DLL (50) for generating a plurality of clock signals including a main clock signal and a clock signal having a different phase

a delay adjustment circuit (20) for delaying the comparison signal by a length equal to or greater than one cycle of the main clock signal

a counter (30) for calculating the time from the start of ramp waveform change to inversion of the output of the comparator on the basis of the output signal from the delay adjustment circuit (20) and the main clock signal, and outputting the time as a high-order bit

and a TDC (40) for latching, decoding, and outputting as a low-order bit the plurality of clock signals generated by the DLL (50) when the output of the delay adjustment circuit (20) is inverted

the TDC (40) starting operation by inversion of the comparison signal, and to stopping operation by inversion of the output signal from the delay adjustment circuit (20).

  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
  • 発明者(英語)
  • IKEBE MASAYUKI
国際特許分類(IPC)
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