FAILURE DETECTION SYSTEM, GENERATING CIRCUIT AND PROGRAM
The purpose of the invention is to provide items such as a failure detection system capable of providing for a reduction in shift power at the time of a scan-out, while maintaining a failure detection rate. The invention is the failure detection system, which by means of a scan test, detects a failure in a logic circuit, said failure detection system being provided with: multiple flip-flops
a final signal generating means that generates a final signal that indicates that a final capture in a capture mode is said final capture
a specification means that is different from both the logic circuit and the flip-flops, and that for a portion of the flip-flops, specifies a logic value if the final signal is received
and a failure detection device that performs a failure detection by making a comparison. Said comparison is between: test output captured from the logic circuit, said test output containing a logic value specified by the specification means
and test output when the logic circuit has not failed, said test output containing a logic value specified by the specification means.