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Flip-flop circuit, semiconductor device and electronic apparatus

外国特許コード F150008344
整理番号 外0083-1
掲載日 2015年5月19日
出願国 アメリカ合衆国
出願番号 201113702638
公報番号 20130082757
公報番号 8581652
出願日 平成23年6月8日(2011.6.8)
公報発行日 平成25年4月4日(2013.4.4)
公報発行日 平成25年11月12日(2013.11.12)
国際出願番号 JP2011063154
国際公開番号 WO2011155532
国際出願日 平成23年6月8日(2011.6.8)
国際公開日 平成23年12月15日(2011.12.15)
優先権データ
  • 特願2010-134066 (2010.6.11) JP
  • 2011JP063154 (2011.6.8) WO
発明の名称 (英語) Flip-flop circuit, semiconductor device and electronic apparatus
発明の概要(英語) A flip-flop circuit (FF 10) of the present invention includes master latch circuits (LAT 11 and LAT 12), slave latch circuits (LAT 13 and LAT 14), C-element circuits (CE 11, CE 12, CE 13, and CE 14), and inverter circuits (INV 11, INV 12, INV 13, and INV 14).
The inverter circuits (INV 11 and INV 12) are interconnected to each other between the C-element circuit (CE 11) and the C-element circuit (CE 12).
The inverter circuits (INV 13 and INV 14) are interconnected to each other between the C-element circuit (CE 13) and the C-element circuit (CE 14).
特許請求の範囲(英語) [claim1]
1. A flip-flop circuit for retaining input data, comprising: a first master latch circuit for latching the input data;
a second master latch circuit for latching the input data;
a first C-element circuit for receiving an inverted output of the first master latch circuit and an inverted output of the second master latch circuit;
a second C-element circuit for receiving a non-inverted output of the first master latch circuit and a non-inverted output of the second master latch circuit;
a first slave latch circuit for latching an output of the first C-element circuit;
a second slave latch circuit for latching an output of the second C-element circuit;
a third C-element circuit for receiving an inverted output of the first slave latch circuit and an inverted output of the second slave latch circuit;
a fourth C-element circuit for receiving a non-inverted output of the first slave latch circuit and a non-inverted output of the second slave latch circuit;
a first inverter circuit;
a second inverter circuit being interconnected to the first inverter circuit;
a third inverter circuit; and
a fourth inverter circuit being interconnected to the third inverter circuit,
an input terminal of the first inverter circuit and an output terminal of the second inverter circuit being connected to a connection point between an output terminal of the first C-element circuit and a data input terminal of the first slave latch circuit,
an output terminal of the first inverter circuit and an input terminal of the second inverter circuit being connected to a connection point between an output terminal of the second C-element circuit and a data input terminal of the second slave latch circuit,
an input terminal of the third inverter circuit and an output terminal of the fourth inverter circuit being connected to an output terminal of the third C-element circuit,
an output terminal of the third inverter circuit and an input terminal of the fourth inverter circuit being connected to an output terminal of the fourth C-element circuit.
[claim2]
2. The flip-flop circuit as set forth in claim 1, further comprising: a delay circuit,
the input data being supplied to the second master latch circuit via the delay circuit.
[claim3]
3. A semiconductor device comprising: a flip-flop circuit recited in claim 2.
[claim4]
4. The flip-flop circuit as set forth in claim 1, wherein: a first node is a node which connects an inverted output terminal of the first master latch circuit and one of input terminals of the first C-element circuit to each other;
a second node is a node which connects an inverted output terminal of the second master latch circuit and the other one of input terminals of the first C-element circuit to each other;
a third node is a node which connects the output terminal of the second C-element circuit, the output terminal of the first inverter circuit, the input terminal of the second inverter circuit, and the data input terminal of the second slave latch circuit to each other;
a fourth node is a node which connects a non-inverted output terminal of the first master latch circuit and one of input terminals of the second C-element circuit to each other;
a fifth node is a node which connects a non-inverted output terminal of the second master latch circuit and the other one of input terminals of the second C-element circuit to each other;
a sixth node is a node which connects the output terminal of the first C-element circuit, the input terminal of the first inverter circuit, the output terminal of the second inverter circuit, and the data input terminal of the first slave latch circuit to each other;
a seventh node is a node which connects an inverted output terminal of the first slave latch circuit and one of input terminals of the third C-element circuit to each other;
an eighth node is a node which connects an inverted output terminal of the second slave latch circuit and the other one of input terminals of the third C-element circuit to each other;
a ninth node is a node which connects the output terminal of the fourth C-element circuit, the output terminal of the third inverter circuit, and the input terminal of the fourth inverter circuit to each other;
a tenth node is a node which connects a non-inverted output terminal of the first slave latch circuit and one of input terminals of the fourth C-element circuit to each other;
an eleventh node is a node which connects a non-inverted output terminal of the second slave latch circuit and the other one of input terminals of the fourth C-element circuit to each other;
a twelfth node is a node which connects the output terminal of the third C-element circuit, the input terminal of the third inverter circuit, and the output terminal of the fourth inverter circuit to each other;
a distance between any two of the first node, the second node, and the third node is not less than 0.86 mu m;
a distance between any two of the fourth node, the fifth node, and the sixth node is not less than 0.86 mu m;
a distance between any two of the seventh node, the eighth node, and the ninth node is not less than 0.86 mu m; and
a distance between any two of the tenth node, the eleventh node, and the twelfth node is not less than 0.86 mu m.
[claim5]
5. A semiconductor device comprising: a flip-flop circuit recited in claim 4.
[claim6]
6. A semiconductor device comprising: a flip-flop circuit recited in claim 1.
[claim7]
7. An electronic device comprising: a semiconductor device recited in claim 6.
[claim8]
8. A flip-flop circuit for retaining input data, comprising: a first master latch circuit for latching the input data;
a second master latch circuit for latching the input data;
a first C-element circuit for receiving an inverted output of the first master latch circuit and an inverted output of the second master latch circuit;
a second C-element circuit for receiving a non-inverted output of the first master latch circuit and a non-inverted output of the second master latch circuit;
a first slave latch circuit for latching an output of the first C-element circuit;
a second slave latch circuit for latching an output of the second C-element circuit;
a third C-element circuit for receiving an inverted output of the first slave latch circuit and an inverted output of the second slave latch circuit;
a first inverter circuit;
a second inverter circuit being interconnected to the first inverter circuit;
a third inverter circuit; and
a fourth inverter circuit being interconnected to the third inverter circuit,
an input terminal of the first inverter circuit and an output terminal of the second inverter circuit being connected to a connection point between an output terminal of the first C-element circuit and a data input terminal of the first slave latch circuit,
an output terminal of the first inverter circuit and an input terminal of the second inverter circuit being connected to a connection point between an output terminal of the second C-element circuit and a data input terminal of the second slave latch circuit,
an input terminal of the third inverter circuit and an output terminal of the fourth inverter circuit being connected to an output terminal of the third C-element circuit.
[claim9]
9. The flip-flop circuit as set forth in claim 8, further comprising: a delay circuit,
the input data being supplied to the second master latch circuit via the delay circuit.
[claim10]
10. A semiconductor device comprising: a flip-flop circuit recited in claim 9.
[claim11]
11. The flip-flop circuit as set forth in claim 8, wherein: a first node is a node which connects an inverted output terminal of the first master latch circuit and one of input terminals of the first C-element circuit to each other;
a second node is a node which connects an inverted output terminal of the second master latch circuit and the other one of input terminals of the first C-element circuit to each other;
a third node is a node which connects the output terminal of the second C-element circuit, the output terminal of the first inverter circuit, the input terminal of the second inverter circuit, and the data input terminal of the second slave latch circuit to each other;
a fourth node is a node which connects a non-inverted output terminal of the first master latch circuit and one of input terminals of the second C-element circuit to each other;
a fifth node is a node which connects a non-inverted output terminal of the second master latch circuit and the other one of input terminals of the second C-element circuit to each other;
a sixth node is a node which connects the output terminal of the first C-element circuit, the input terminal of the first inverter circuit, the output terminal of the second inverter circuit, and the data input terminal of the first slave latch circuit to each other;
a seventh node is a node which connects an inverted output terminal of the first slave latch circuit and one of input terminals of the third C-element circuit to each other;
an eighth node is a node which connects an inverted output terminal of the second slave latch circuit and the other one of input terminals of the third C-element circuit to each other;
a ninth node is a node which connects the output terminal of the third inverter circuit and the input terminal of the fourth inverter circuit;
a distance between any two of the first node, the second node, and the third node is not less than 0.86 mu m;
a distance between any two of the fourth node, the fifth node, and the sixth node is not less than 0.86 mu m; and
a distance between any two of the seventh node, the eighth node, and the ninth node is not less than 0.86 mu m.
[claim12]
12. A semiconductor device comprising: a flip-flop circuit recited in claim 11.
[claim13]
13. A semiconductor device comprising: a flip-flop circuit recited in claim 8.
[claim14]
14. An electronic device comprising: a semiconductor device recited in claim 13.
[claim15]
15. A flip-flop circuit for retaining input data, comprising: a first master latch circuit for latching the input data;
a second master latch circuit for latching the input data;
a first C-element circuit for receiving an inverted output of the first master latch circuit and an inverted output of the second master latch circuit;
a second C-element circuit for receiving a non-inverted output of the first master latch circuit and a non-inverted output of the second master latch circuit;
a first slave latch circuit for latching an output of the first C-element circuit;
a second slave latch circuit for latching an output of the second C-element circuit;
a fourth C-element circuit for receiving a non-inverted output of the first slave latch circuit and a non-inverted output of the second slave latch circuit;
a first inverter circuit;
a second inverter circuit being interconnected to the first inverter circuit;
a third inverter circuit; and
a fourth inverter circuit being interconnected to the third inverter circuit,
an input terminal of the first inverter circuit and an output terminal of the second inverter circuit being connected to a connection point between an output terminal of the first C-element circuit and a data input terminal of the first slave latch circuit,
an output terminal of the first inverter circuit and an input terminal of the second inverter circuit being connected to a connection point between an output terminal of the second C-element circuit and a data input terminal of the second slave latch circuit,
an output terminal of the third inverter circuit and an input terminal of the fourth inverter circuit being connected to an output terminal of the fourth C-element circuit.
[claim16]
16. The flip-flop circuit as set forth in claim 15, further comprising: a delay circuit,
the input data being supplied to the second master latch circuit via the delay circuit.
[claim17]
17. A semiconductor device comprising: a flip-flop circuit recited in claim 16.
[claim18]
18. The flip-flop circuit as set forth in claim 15, wherein: a first node is a node which connects an inverted output terminal of the first master latch circuit and one of input terminals of the first C-element circuit to each other;
a second node is a node which connects an inverted output terminal of the second master latch circuit and the other one of input terminals of the first C-element circuit to each other;
a third node is a node which connects the output terminal of the second C-element circuit, the output terminal of the first inverter circuit, the input terminal of the second inverter circuit, and the data input terminal of the second slave latch circuit to each other;
a fourth node is a node which connects a non-inverted output terminal of the first master latch circuit and one of input terminals of the second C-element circuit to each other;
a fifth node is a node which connects a non-inverted output terminal of the second master latch circuit and the other one of input terminals of the second C-element circuit to each other;
a sixth node is a node which connects the output terminal of the first C-element circuit, the input terminal of the first inverter circuit, the output terminal of the second inverter circuit, and the data input terminal of the first slave latch circuit to each other;
a tenth node is a node which connects a non-inverted output terminal of the first slave latch circuit and one of input terminals of the fourth C-element circuit to each other;
an eleventh node is a node which connects a non-inverted output terminal of the second slave latch circuit and the other one of input terminals of the fourth C-element circuit to each other;
a twelfth node is a node which connects the input terminal of the third inverter circuit and the output terminal of the fourth inverter circuit to each other;
a distance between any two of the first node, the second node, and the third node is not less than 0.86 mu m;
a distance between any two of the fourth node, the fifth node, and the sixth node is not less than 0.86 mu m; and
a distance between any two of the tenth node, the eleventh node, and the twelfth node is not less than 0.86 mu m.
[claim19]
19. A semiconductor device comprising: a flip-flop circuit recited in claim 18.
[claim20]
20. A semiconductor device comprising: a flip-flop circuit recited in claim 15.
  • 発明者/出願人(英語)
  • KOBAYASHI KAZUTOSHI
  • FURUTA JUN
  • ONODERA HIDETOSHI
  • KYOTO INSTITUTE OF TECHNOLOGY
国際特許分類(IPC)
米国特許分類/主・副
  • 327/202
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