TOP > 外国特許検索 > RECONFIGURABLE DELAY CIRCUIT, DELAY MONITOR CIRCUIT USING SAID DELAY CIRCUIT, VARIATION CORRECTION CIRCUIT, VARIATION MEASUREMENT METHOD, AND VARIATION CORRECTION METHOD

RECONFIGURABLE DELAY CIRCUIT, DELAY MONITOR CIRCUIT USING SAID DELAY CIRCUIT, VARIATION CORRECTION CIRCUIT, VARIATION MEASUREMENT METHOD, AND VARIATION CORRECTION METHOD

外国特許コード F150008480
掲載日 2015年10月26日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2014JP069976
国際公開番号 WO 2015025682
国際出願日 平成26年7月29日(2014.7.29)
国際公開日 平成27年2月26日(2015.2.26)
優先権データ
  • 特願2013-169965 (2013.8.19) JP
発明の名称 (英語) RECONFIGURABLE DELAY CIRCUIT, DELAY MONITOR CIRCUIT USING SAID DELAY CIRCUIT, VARIATION CORRECTION CIRCUIT, VARIATION MEASUREMENT METHOD, AND VARIATION CORRECTION METHOD
発明の概要(英語) A delay circuit (10) containing a first inverting circuit, which contains a pull-up circuit (2) and a pull-down circuit (3), and a second inverting circuit, which contains a pull-up circuit (4) and a pull-down circuit (5). The delay circuit also contains: a first pass transistor (6) connected in series to the pull-up circuit of the first inverting circuit between a power supply potential and an output node; a second pass transistor (7) connected in series to the pull-down circuit (2) of the first inverting circuit between a ground potential and the output node (Out); a third pass transistor (8) inserted in series between an input node (In) and the pull-up circuit of the second inverting circuit; and a fourth pass transistor (9) inserted in series between the input node and the pull-down circuit of the second inverting circuit. The delay characteristic of the delay circuit is changed by a combination of control signals (C1-C4) applied to the gates of the first - fourth pass transistors.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • ONODERA HIDETOSHI
  • A K M MAHFUZUL ISLAM
国際特許分類(IPC)
指定国 National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KZ LA LC LK LR LS LT LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN TD TG
参考情報 (研究プロジェクト等) CREST Fundamental Technologies for Dependable VLSI System AREA
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