TOP > 外国特許検索 > Reconfigurable delay circuit, delay monitor circuit using said delay circuit, variation correction circuit, variation measurement method, and variation correction method

Reconfigurable delay circuit, delay monitor circuit using said delay circuit, variation correction circuit, variation measurement method, and variation correction method

外国特許コード F150008515
整理番号 AF14-01TW
掲載日 2015年11月19日
出願国 台湾
出願番号 103126689
公報番号 201526547
公報番号 I548221
出願日 平成26年8月5日(2014.8.5)
公報発行日 平成27年7月1日(2015.7.1)
公報発行日 平成28年9月1日(2016.9.1)
優先権データ
  • 特願2013-169965 (2013.8.19) JP
発明の名称 (英語) Reconfigurable delay circuit, delay monitor circuit using said delay circuit, variation correction circuit, variation measurement method, and variation correction method
発明の概要(英語) A delay circuit (10) containing a first inverting circuit, which contains a pull-up circuit (2) and a pull-down circuit (3), and a second inverting circuit, which contains a pull-up circuit (4) and a pull-down circuit (5).
The delay circuit also contains: a first pass transistor (6) connected in series to the pull-up circuit of the first inverting circuit between a power supply potential and an output node; a second pass transistor (7) connected in series to the pull-down circuit (2) of the first inverting circuit between a ground potential and the output node (Out); a third pass transistor (8) inserted in series between an input node (In) and the pull-up circuit of the second inverting circuit; and a fourth pass transistor (9) inserted in series between the input node and the pull-down circuit of the second inverting circuit.
The delay characteristic of the delay circuit is changed by a combination of control signals (C1-C4) applied to the gates of the first - fourth pass transistors.
特許請求の範囲(英語) [claim1]

(Claims machine translated from Chinese)
[claim2]
1. Kinds of delay circuits, are contains in the detention monitor circuit may the heavy configuration delay circuit, this detention monitor circuit to be used to determine the microcircuit postponer in of signaling time, its characteristic is, has: Input node, for inputting input signal;
Output node, for outputting output signal;
The 1st reverse electric circuit, its contains to pull the electric circuit to pull the electric circuit with below the series circuit, should get up to pull the electric circuit, when supposed based on the above input signal is ON is the power source electric potential connection in the output node, should get down to pull the electric circuit, when supposed based on the above input signal is ON is the earth electric potential connection in the above output node;
The 2nd reverse electric circuit, its contains to pull the electric circuit to pull the electric circuit with below the series circuit, should get up to pull the electric circuit, when supposed based on the above input signal is ON is the power source electric potential connection in the output node, should get down to pull the electric circuit, when supposed based on the above input signal is ON is the earth electric potential connection in the above output node;
The 1st circuit transistor, is in the above power source electric potential with the above output nodes, with the above 1st reverse electric circuit on pulls the electric circuit to assume the series connection;
The 2nd circuit transistor, is in the above earth electric potential with the above output nodes, with the above 1st reverse electric circuit below pulls the electric circuit to assume the series connection;
The 3rd circuit transistor, was pulled in the above input node with the above 2nd reverse electric circuit above by the series connection the inputs of electric circuit;
And the 4th circuit transistor, was pulled in the above input node with the above 2nd reverse electric circuit under by the series connection the inputs of electric circuit;
Because to above changes the delay characteristic 1st to combination that of the control signal the floodgate of 4th circuit transistor exerts extremely.
[claim3]
2. Like request item of 1 delay circuit, at least seperately connects the 5th circuit transistor by the parallel way in the above 3rd circuit transistor, at least seperately connects the 6th circuit transistor by the parallel way in the above 4th circuit transistor.
[claim4]
3. Like request item of 1 delay circuit, seperately has: The 7th circuit transistor, is connection pulls the electric circuits and above power source electric potentials between the above 2nd reverse electric circuit;
And the 8th circuit transistor, is the connection pulls the electric circuits and above earth electric potentials between the above 2nd reverse electric circuit.
[claim5]
4. Like request item of 1 delay circuit, seperately has: The 7th circuit transistor, is connection between the above 2nd reverse electric circuit on pulls of control inputs and above power source electric potentials electric circuit;
And the 8th circuit transistor, is the connection between the above 2nd reverse electric circuit below pulls of control inputs and above earth electric potentials electric circuit.
[claim6]
5. Like request item of 1 delay circuit, the combination of above control signal, is includes: Supposes above 1st and 2nd circuit transistor is ON, supposes above 3rd and 4th circuit transistor is OFF combination of the control signal;
Supposes above 1st and 4th circuit transistor is ON, supposes above 2nd and 3rd circuit transistor is OFF combination of the control signal;
And supposes above 2nd and 3rd circuit transistor is ON, supposes above 1st and 4th circuit transistor is OFF combination of the control signal.
[claim7]
6. Like request item 1 to five any item of delay circuit, the above 1st circuit transistor, is the series connection in the above power source electric potential with the above 1st reverse electric circuit on pulls the electric circuits, the above 2nd circuit transistor, is the series connection in the above earth electric potential with the above 1st reverse electric circuit below pulls the electric circuits.
[claim8]
7. Like request item 1 to five any item of delay circuit, the above 1st circuit transistor, is the series connection in the above 1st reverse electric circuit on pulls the electric circuit with the above output nodes, the above 2nd circuit transistor, is the series connection in the above output node with the above 1st reverse electric circuit below pulls the electric circuits.
[claim9]
8. Like request item 1 to five any item of delay circuit, above on pulls the electric circuit and above 3rd circuit transistor is by the pMOS transistor constitution, above under pulls the electric circuit and above 4th circuit transistor is constitutes by the nMOS transistor.
[claim10]
9. 1 kinds of detention monitor circuits, are for determining microcircuit the electric circuit in of detention of signaling time, its characteristic to include: Like request item 1 in five any delay circuit plural number section series connection to the electric circuit that becomes.
[claim11]
10. Like request item of 9 detention monitor circuits, the output of final section delay circuit is returns to give to the input of 1st section of delay circuit.
[claim12]
11. 1 kinds of deviation correcting circuits, are in circuit element's the characteristic deviation to the microcircuit carry on the reviser, has: If requested the item of 9 detention monitor circuits;
And the correcting circuit, is revises the above circuit element's characteristic deviation based on the signaling detention of above detention monitor circuit determination.
[claim13]
12. Like request item of 11 deviation correcting circuits, the above circuit element is a transistor, the above correcting circuit, is changes the foundation plate of voltage above transistor based on the signaling detention of above determination, according to this, but carries on the revision to the above transistor's characteristic.
[claim14]
13. 1 determination methods, are use in the detention monitor circuit determination microcircuit circuit element's characteristic deviation;
The above detention monitor circuit contains the electric circuit that like the request 1 delay circuit plural number section series connection will become;
The above determination method, is includes: In order to make specific section constitution of the delay circuit, outside section the delay circuit with this specific section constitutes into the different way in various hypothesis control signals, and exerts in the 1st step of above circuit transistor;
Under exerting the above control signal condition, carries on determination to the output of above detention monitor circuit the 2nd step;
The change above specific section at the same time, repeatedly carries on the above 1st step and 2nd step 3rd step in order;
And based on the determination result that the above 3rd step obtains, in view of for forming in the above microcircuit's chip circuit element's the characteristic deviation carries on determination the 4th step.
[claim15]
14. 1 determination methods, are use the detention monitor circuit in view of among forming microcircuit's semiconductor chips circuit element's the characteristic deviation carry on the determination the method, the above detention monitor circuit contains the electric circuit that like the request 1 delay circuit plural number section series connection will become;
The above determination method, is includes: In order to enable complete section delay circuit to constitute into the same way, and exerts in various hypothesis control signals in the 1st step of above circuit transistor;
Under exerting the above control signal condition, carries on determination in view of the output of above detention monitor circuit the 2nd step;
And based on the determination result that the above 2nd step obtains, in view of among forming the above microcircuit's chips circuit element's the characteristic deviation carries on determination the 3rd step.
[claim16]
15. 1 determination methods, are use in the detention monitor circuit determination microcircuit circuit element's characteristic deviation;
The above detention monitor circuit contains the electric circuit that like the request 2 delay circuit plural number section series connection will become;
The above determination method, is includes: In order to make specific section constitution of the delay circuit, outside section the delay circuit with this specific section constitutes into the different way, and exerts in various hypothesis control signals in the 1st step of above circuit transistor;
Under exerting the above control signal condition, carries on determination to the output of above detention monitor circuit the 2nd step;
The change above specific section at the same time, repeatedly carries on the above 1st step and 2nd step 3rd step in order;
And based on the determination result that the above 3rd step obtains, in view of for forming in the above microcircuit's chip circuit element's the characteristic deviation carries on determination the 4th step;
The above 2nd step, is includes: In view of the above specific section, supposes the above 3rd circuit transistor is ON, supposes the above 5th circuit transistor is OFF, but carries on determination to the output of above detention monitor circuit the 5th step;
In the above specific section, supposes the above 3rd circuit transistor is OFF, supposes the above 5th circuit transistor is ON, but carries on determination to the output of above detention monitor circuit the 6th step;
And carries on computation with the determination of result's above 6th step difference in view of the determination of result above 5th step the 7th step.
[claim17]
16. 1 determination methods, are use in the detention monitor circuit determination microcircuit circuit element's characteristic deviation;
The above detention monitor circuit contains the electric circuit that like the request 2 delay circuit plural number section series connection will become;
The above determination method, is includes: In order to make specific section constitution of the delay circuit, outside section the delay circuit with this specific section constitutes into the different way, and exerts in various hypothesis control signals in the 1st step of above circuit transistor;
Under exerting the above control signal condition, carries on determination to the output of above detention monitor circuit the 2nd step;
The change above specific section at the same time, repeatedly carries on the above 1st step and 2nd step 3rd step in order;
And based on the determination result that the above 3rd step obtains, in view of for forming in the above microcircuit's chip circuit element's the characteristic deviation carries on determination the 4th step;
The above 2nd step, is includes: In view of the above specific section, supposes the above 4th circuit transistor is ON, supposes the above 6th circuit transistor is OFF, but carries on determination to the output of above detention monitor circuit the 5th step;
In the above specific section, supposes the above 4th circuit transistor is OFF, supposes the above 6th circuit transistor is ON, but carries on determination to the output of above detention monitor circuit the 6th step;
And carries on computation with the determination of result's above 6th step difference in view of the determination of result above 5th step the step.
[claim18]
17. 1 deviation compliance solutions, have: The use like request item in circuit element's the characteristic deviation in view of the microcircuit carry on determination 13 to 16 any determination method the step;
And in view of above circuit element's characteristic carries on revision based on deviation that the above determination obtains the step.
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • ONODERA HIDETOSHI
  • A K M MAHFUZUL ISLAM
国際特許分類(IPC)
参考情報 (研究プロジェクト等) CREST Fundamental Technologies for Dependable VLSI System AREA
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