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MEMORY CIRCUIT

外国特許コード F160008740
整理番号 (AF15P011)
掲載日 2016年5月20日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2015JP072392
国際公開番号 WO 2016024527
国際出願日 平成27年8月6日(2015.8.6)
国際公開日 平成28年2月18日(2016.2.18)
優先権データ
  • 特願2014-164526 (2014.8.12) JP
発明の名称 (英語) MEMORY CIRCUIT
発明の概要(英語) A memory circuit characterized by comprising a plurality of cells and a control unit, as follows. The plurality of cells are laid out in a plurality of rows and a plurality of columns so as to form a plurality of banks obtained by partitioning the plurality of rows. Each bank contains one or more rows. Each cell comprises the following: a bistable circuit that holds data; and a nonvolatile element that stores, in a nonvolatile manner, the data held in the bistable circuit and restores said data to the bistable circuit. The control unit: performs a store operation on each row in turn; sets, to a first voltage, the voltage supplied to a power supply for the cells in a first bank that is one of the abovementioned banks and includes the row on which the aforementioned store operation is being performed; and sets, to a second voltage that is lower than the aforementioned first voltage but at which the data in the bistable circuits is preserved, the voltages supplied to power supplies for cells that are not in the aforementioned first bank.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • KANAGAWA ACADEMY OF SCIENCE AND TECHNOLOGY
  • 発明者(英語)
  • SUGAHARA SATOSHI
  • SHUTO YUSUKE
  • YAMAMOTO SHUICHIRO
国際特許分類(IPC)
指定国 National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
参考情報 (研究プロジェクト等) CREST Research of Innovative Material and Process for Creation of Next-generation Electronics Devices AREA
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