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Method for manufacturing silicon-carbide semiconductor element

外国特許コード F160008778
整理番号 KG0119-US01
掲載日 2016年8月3日
出願国 アメリカ合衆国
出願番号 201414897380
公報番号 20160111279
出願日 平成26年6月6日(2014.6.6)
公報発行日 平成28年4月21日(2016.4.21)
国際出願番号 JP2014003048
国際公開番号 WO2014199614
国際出願日 平成26年6月6日(2014.6.6)
国際公開日 平成26年12月18日(2014.12.18)
優先権データ
  • 特願2013-125018 (2013.6.13) JP
  • 2014JP003048 (2014.6.6) WO
発明の名称 (英語) Method for manufacturing silicon-carbide semiconductor element
発明の概要(英語) In this method for manufacturing a semiconductor element, a modified layer produced by subjecting a substrate (70) to mechanical polishing is removed by heating the substrate (70) under Si vapor pressure.
An epitaxial layer formation step, an ion implantation step, an ion activation step, and a second removal step are then performed.
In the second removal step, macro-step bunching and insufficient ion-implanted portions of the surface of the substrate (70) performed the ion activation step are removed by heating the substrate (70) under Si vapor pressure.
After that, an electrode formation step in which electrodes are formed on the substrate (70) is performed.
従来技術、競合技術の概要(英語) BACKGROUND ART
[0002] Silicon (Si), gallium arsenide (GaAs), and the like, are conventionally known as a semiconductor material.
Recently, the field of use of the semiconductor material is rapidly expanding.
The semiconductor material is accordingly more often used under severe environments such as a high temperature environment.
Therefore, achievement of the semiconductor material that is able to withstand a high temperature environment is one of important problems from the viewpoint of a reliable operation, processing of a large amount of information, and improvement in the controllability in wide ranges of applications and environments.
[0003] Silicon carbide (SiC) is of interest as one of materials that can be used for manufacturing a semiconductor element having an excellent heat resistance.
SiC has an excellent mechanical strength and a radiation hardness.
Moreover, adding impurities to SiC enables a valence electron such as an electron or a hole to be easily controlled, and SiC is characterized in a wide band gap (about 3.0 eV in 6H single crystal SiC; 3.2 eV in 4H single crystal SiC).
This is why SiC is expected as a material for a next-generation power device that achieves a high-temperature resistance, high frequency resistance, high voltage resistance, and high environment resistance, which cannot be achieved by the existing semiconductor material described above.
Methods for manufacturing a semiconductor material using SiC are disclosed in Patent Documents 1 to 3.
[0004] Patent Document 1 discloses a method for manufacturing a SiC semiconductor having high quality, when generation of SiC polycrystalline is suppressed by uniformizing the temperature in a growth furnace causing a growth of a seed crystal.
Patent Document 2 discloses a method for manufacturing a SiC semiconductor having little defect and high quality by forming a plurality of recesses in a seed crystal.

PRIOR-ART DOCUMENTS

Patent Documents
[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2012-193055
[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2012-176867

特許請求の範囲(英語) [claim1]
1. A method for manufacturing a semiconductor element using a substrate having an off angle, the substrate having at least its surface made of a SiC layer, the method comprising: a first removal step of removing a modified layer produced by subjecting the substrate to mechanical polishing by heating the substrate under Si vapor pressure;
an epitaxial layer formation step of forming an epitaxial layer on the substrate that is the modified layer is removed;
an ion implantation step of implanting ions on the epitaxial layer;
an ion activation step of activating ions by heating the substrate;
a second removal step of removing at least one insufficient ion-implanted portion of the surface of the substrate that is the ion activation step is performed thereon and a macro-step bunching occurred on the surface of the substrate during the ion activation step by heating the substrate under Si vapor pressure; and
an electrode formation step of forming at least one electrode on the substrate from which at least one insufficient ion-implanted portion and macro-step bunching are removed by the second removal step.
[claim2]
2. The method for manufacturing the semiconductor element according to claim 1, wherein in the first removal step, heating is performed in a temperature range of 1800 deg. C. or more and 2300 deg. C. or less and under Si pressure of 10-2 Pa or more.
[claim3]
3. The method for manufacturing the semiconductor element according to claim 1, wherein in the epitaxial layer formation step, an epitaxial layer is formed using a chemical vapor deposition method.
[claim4]
4. The method for manufacturing the semiconductor element according to claim 1, wherein in the epitaxial layer formation step, an epitaxial layer is formed using a liquid-phase epitaxial method.
[claim5]
5. The method for manufacturing the semiconductor element according to claim 1, wherein in the ion activation step, heating is performed in a temperature range of 1800 deg. C. or more and 2300 deg. C. or less and under Si pressure of 10-3 Pa or less.
[claim6]
6. The method for manufacturing the semiconductor element according to claim 1, wherein in the second removal step, heating is performed in a temperature range of 1600 deg. C. or more and 2000 deg. C. or less and under Si pressure of 10-3 Pa or less.
[claim7]
7. The method for manufacturing the semiconductor element according to claim 1, wherein the surface of the SiC layer has an off angle of 4 degrees or less in the direction of <11-20>.
[claim8]
8. The method for manufacturing the semiconductor element according to claim 1, wherein the surface of the SiC layer has an off angle of 4 degrees or less in the direction of <1-100>.
[claim9]
9. The method for manufacturing the semiconductor element according to claim 1, wherein the surface of the SiC layer terminates at a step having a full-unit height that corresponds to one periodic of SiC molecules in a stack direction or a half-unit height that corresponds to one-half periodic thereof.
[claim10]
10. The method for manufacturing the semiconductor element according to claim 1, wherein the electrode formation step and the second removal step are continuously performed using a common heating apparatus.
[claim11]
11. The method for manufacturing the semiconductor element according to claim 1, wherein in consideration of the relationship between heating condition including Si pressure, heating temperature, and etching rate and the presence or absence of occurrence of macro-step bunching, heating condition is determined in at least either one of the first removal step or the second removal step.
  • 発明者/出願人(英語)
  • KANEKO TADAAKI
  • OHTANI NOBORU
  • HAGIWARA KENTA
  • KWANSEI GAKUIN
国際特許分類(IPC)
米国特許分類/主・副
  • 438/492
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