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FIELD-EFFECT TRANSISTOR

外国特許コード F160008790
整理番号 (AF15P014)
掲載日 2016年8月4日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2015JP004902
国際公開番号 WO 2016059754
国際出願日 平成27年9月28日(2015.9.28)
国際公開日 平成28年4月21日(2016.4.21)
優先権データ
  • 特願2014-211575 (2014.10.16) JP
発明の名称 (英語) FIELD-EFFECT TRANSISTOR
発明の概要(英語) A field-effect transistor (100) is provided with a channel (30c) formed of a semiconductor nano wire (30). A source region (30s) and a drain region (30d) are formed adjacent to the channel (30c), and a gate electrode (40) is provided above the channel. On the main surface of the semiconductor nano wire (30), a mask layer (50) is provided, said mask layer containing dopant atoms to be a donor or an acceptor. Though the dopant atoms are ion-implanted into the mask layer (50) on a side wall portion of the gate electrode (40) as well, the implanted ions stay at an upper portion, and are not implanted as far as to a portion in contact with the main surface of the semiconductor nano wire (30). Consequently, a mask layer portion formed with a thickness W on the side wall of the gate electrode (40) does not function as a diffusion source of the dopant.
特許請求の範囲(英語) [claim1]
1.  And the thickness was formed by the semiconductor material portion of the H (nm) channel, a source region and a drain region formed adjacent to the channel, a field effect transistor having a gate region disposed above the channel there,  Gate length of the gate region (Lg) is 10nm or less in 4nm or more,  Number dopant atoms in the central region of the channel is 1 or less, Field-effect transistor.
[2]
[claim2]
2.  And the thickness was formed by the semiconductor material portion of the H (nm) channel, a source region and a drain region formed adjacent to the channel, a field effect transistor having a gate region disposed above the channel there,  The provided on the main surface of the semiconductor material portion, a mask layer including a dopant atom which serves as a donor or acceptor, the thickness of the side wall of the gate electrode provided on the gate region comprises a mask layer of W (nm) ,  The mask layer is coated with a main surface portion of the semiconductor material region where the source region and the drain region is formed,  Gate length of the gate region (Lg) is 10nm or less in 4nm or more,  The thickness W of the mask layer of the sidewalls of the gate electrode (nm) is in the range of [3H-2] / 7 + [10-Lg] / 2 ≦ W ≦ [3H + 19] / 7, Field-effect transistor.
[3]
[claim3]
3.  Number dopant atoms in the central region of the channel is 1 or less, The field effect transistor of claim 2.
[4]
[claim4]
4.  The dopant concentration of the source region and 2nm region to the drain region side from an end portion of the channel, is 5 × 10 <19> cm <-3> or more, in any one of claims 1 to 3, field effect transistor according.
[5]
[claim5]
5.  The semiconductor material portion may comprise silicon, germanium, made from any material of group III-V compound semiconductor, field-effect transistor according to any one of claims 1-4.
[6]
[claim6]
6.  Said semiconductor material region is made of silicon, the mask layer is a silicon oxide film or a silicide film, the field effect transistor of claim 5.
[7]
[claim7]
7.  It said dopant is phosphorus, antimony, arsenic, boron, aluminum, indium, or gallium, the field effect transistor of claim 6.
[8]
[claim8]
8.  Said semiconductor material region is made of germanium, said mask layer is a germanium oxide or germanide film field effect transistor according to claim 5.
[9]
[claim9]
9.  It said dopant is phosphorus, antimony, arsenic, boron, aluminum, indium, or gallium, the field effect transistor of claim 8.
[10]
[claim10]
10.  It said semiconductor material region comprises a Group III-V compound semiconductor, wherein the mask layer is a silicon oxide film, a field effect transistor of claim 5.
[11]
[claim11]
11.  Wherein the dopant is either zinc, silicon, beryllium, the field effect transistor according to claim 10.
[12]
[claim12]
12.  The semiconductor material portion, silicon nanowires, germanium nanowires, either a group III-V compound semiconductor nanowire field effect transistor according to any one of claims 1-4.
[13]
[claim13]
13.  Thickness A method of manufacturing a field effect transistor comprising a channel formed by the semiconductor material portion of the H (nm),  Above the channel, the steps of the gate length (Lg) to form a gate electrode so that the 10nm or less 4nm or more,  It said gate electrode, and, a mask layer covering the main surface portion of the semiconductor material region a source region and a drain region adjacent to the channel is formed, the thickness of the side walls of the gate electrode is at W (nm) forming a mask layer,  A step of implanting dopant atoms that serves as a donor or an acceptor in the mask layer,  The implanted the dopant atoms in the mask layer, and a step of diffusing the source region and the drain region,  The thickness W (nm) of the mask layer of the sidewall of the gate electrode is set to a range of [3H-2] / 7 + [10-Lg] / 2 ≦ W ≦ [3H + 19] / 7, Method for manufacturing a field effect transistor.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • UEMATSU MASASHI
  • ITOH KOHEI
  • MORI NOBUYA
国際特許分類(IPC)
指定国 National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
参考情報 (研究プロジェクト等) CREST Research of Innovative Material and Process for Creation of Next-generation Electronics Devices AREA
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