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SEMICONDUCTOR INTEGRATED CIRCUIT AND DELAY MEASUREMENT CIRCUIT

外国特許コード F160008877
整理番号 (S2015-0412-N0)
掲載日 2016年10月25日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2016JP001185
国際公開番号 WO 2016139958
国際出願日 平成28年3月4日(2016.3.4)
国際公開日 平成28年9月9日(2016.9.9)
優先権データ
  • 特願2015-044113 (2015.3.5) JP
発明の名称 (英語) SEMICONDUCTOR INTEGRATED CIRCUIT AND DELAY MEASUREMENT CIRCUIT
発明の概要(英語) A semiconductor integrated circuit according to one aspect of the present invention is provided with: a circuit unit to be measured provided with a plurality of connected flip-flop circuits; a clock generation circuit unit; and a delay measurement circuit unit which is provided with a NAND circuit, a plurality of NOT circuits connected in series with the NAND circuit, a counter circuit connected to terminals of the plurality of NOT circuits, and a scan chain circuit in which a plurality of selector circuits and a plurality of flip-flop circuits are connected. The NAND circuit is provided with at least two bias voltage input gates.
特許請求の範囲(英語) [claim1]
1. Clock formation circuit and,
The counter circuit which is connected to the end of the plural delay circuits and the aforementioned plural delay circuits which are connected in series to the fan out circuit and the aforementioned fan out circuit and, the delay measurement circuit which it possesses and, being the delay measurement circuit which it has,
At least one of the aforementioned fan out circuit and the aforementioned plural delay circuits the delay measurement circuit which is delay time variable.
[claim2]
2. As for the aforementioned fan out circuit, the delay measurement circuit of the claim 1 statement which includes at least either the NAND circuit and the NOR circuit.
[claim3]
3. As for the aforementioned delay circuit, the delay measurement circuit of the claim 1 statement which includes at least either the NOT circuit and the buffer circuit.
[claim4]
4. The delay measurement circuit of the claim 1 statement which has the scan chain circuit where the plural selector circuits and the plural flip-flop circuits are connected.
[claim5]
5. Suffering measurement circuit and,
Clock formation circuit and,
The counter circuit which is connected to the end of the plural delay circuits and the aforementioned plural delay circuits which are connected in series to the fan out circuit and the aforementioned fan out circuit and, the delay measurement circuit which it possesses and, being the semiconductor integrated circuit which it has,
At least one of the aforementioned fan out circuit and the aforementioned plural delay circuits the semiconductor integrated circuit which at least has two bias voltage input gates.
[claim6]
6. As for the aforementioned fan out circuit, the semiconductor integrated circuit of the claim 5 statement which includes at least either the NAND circuit and the NOR circuit.
[claim7]
7. As for the aforementioned delay circuit, the semiconductor integrated circuit of the claim 5 statement which includes at least either the NOT circuit and the buffer circuit.
[claim8]
8. The semiconductor integrated circuit of the claim 5 statement which has the scan chain circuit where the plural selector circuits and the plural flip-flop circuits are connected.
[claim9]
9. The suffering measurement circuit which possesses the plural flip-flop circuits which are connected and,
Clock formation circuit and,
The scan chain circuit where the counter circuit and the plural selector circuits and the plural flip-flop circuits which are connected to the end of the plural NOT circuits and the plural aforementioned NOT circuits which are connected in series to the NAND circuit and the aforementioned NAND circuit are connected and, the delay measurement circuit which it possesses and, being the semiconductor integrated circuit which it has,
As for the aforementioned NAND circuit, the semiconductor integrated circuit which at least has two bias voltage input gates.
[claim10]
10. The scan chain circuit where the counter circuit and the plural selector circuits and the plural flip-flop circuits which are connected to the end of the plural NOT circuits and the plural aforementioned NOT circuits which are connected in series to the NAND circuit and the aforementioned NAND circuit are connected and, having,
As for the aforementioned NAND circuit, the delay measurement circuit which at least has two bias voltage input gates.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • CHIBA UNIVERSITY
  • 発明者(英語)
  • NAMBA KAZUTERU
  • CUI RI
国際特許分類(IPC)
指定国 National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG

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