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ANALOG TO DIGITAL CONVERTER

外国特許コード F170009008
整理番号 (S2015-1988-N33)
掲載日 2017年3月29日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2016JP072724
国際公開番号 WO 2017029984
国際出願日 平成28年8月3日(2016.8.3)
国際公開日 平成29年2月23日(2017.2.23)
優先権データ
  • 特願2015-162086 (2015.8.19) JP
発明の名称 (英語) ANALOG TO DIGITAL CONVERTER
発明の概要(英語) The objective of the present invention is to make it possible to perform high-speed AD conversion using a small surface area and low power consumption, by reducing the number of bits in a single-slope AD converter. To this end, according to the present invention, AD conversion is performed using a combination of: a parallel AD converter (12) which uses a plurality of comparators to compare the input potential of an analog input signal sampled using a track and hold circuit (11) with mutually different reference potentials to determine the values of a predetermined number of higher-order bits of a digital signal; and a single-slope AD converter (13) which reduces at a constant rate the input potential of the analog input signal sampled by the track and hold circuit, and converts to a digital value the time taken for the potential to equal the reference potential corresponding to the value determined by the parallel AD converter, thereby determining the remaining lower-order values of the digital signal.
特許請求の範囲(英語) [claim1]
1. Being the analog digital transmitter which converts the analog input signal which is input to the digital signal,
The track/truck and the hold circuit which sample the aforementioned analog input signal and,
The parallel type analog digital transmitter which possesses the plural comparators to which the input electric potential which responds to the aforementioned analog input signal which is sampled and the reference electric potential which differs mutually are input, compare with the aforementioned input electric potential and the aforementioned reference electric potential, decides the value of specified bit number of superior side of the aforementioned digital signal on the basis of the output of the aforementioned plural comparators and,
Until it keeps decreasing the aforementioned input electric potential which responds to the aforementioned analog input signal which is sampled at fixed speed, the aforementioned reference electric potential which corresponds to the value which is decided with the aforementioned parallel type analog digital transmitter equal it becomes, converting time to digital value, the analog digital transmitter which features that it possesses the single slope type analog digital transmitter which decides the value of remaining subordinate side of the aforementioned digital signal.
[claim2]
2. After the aforementioned single slope type analog digital transmitter starting to decrease the aforementioned input electric potential which responds to the aforementioned analog input signal, until either among outputs of the aforementioned plural comparators which the aforementioned parallel type analog digital transmitter has one output transits, until time, the aforementioned reference electric potential it becomes equal, the analog digital transmitter of the claim 1 statement which features that it makes time.
[claim3]
3. Being the analog digital transmitter which converts the analog input signal which is input to the digital signal,
The track/truck and the hold circuit which sample the aforementioned analog input signal and,
The lamp circuit which decreases the input electric potential which responds to the aforementioned analog input signal which is sampled at fixed speed and,
The plural comparators to which the aforementioned input electric potential and the reference electric potential which differs mutually are input, compare with the aforementioned input electric potential and the aforementioned reference electric potential and,
When having decreased the aforementioned input electric potential by the aforementioned lamp circuit, the detector which detects the output which is transited most quickly among outputs of the aforementioned plural comparators, decides the value of specified bit number of superior side of the aforementioned digital signal on the basis of the detection result and,
After starting to decrease the aforementioned input electric potential by the aforementioned lamp circuit, until the aforementioned detector detects the output which the description above it transits most quickly, converting time to digital value, the time when it decides the value of remaining subordinate side of the aforementioned digital signal - the analog digital transmitter which features that it possesses the digital transmitter.
[claim4]
4. In the aforementioned comparator where 1st reference electric potential among plural aforementioned reference electric potential is input, it differs from the aforementioned 1st reference electric potential, changing 2nd reference electric potential among the aforementioned plural reference electric potential, into the aforementioned input electric potential, the switch in order to input and,
When the aforementioned 2nd reference electric potential which is input into the aforementioned comparator keeping decreasing at fixed speed by the aforementioned lamp circuit, the analog digital transmitter of the claim 3 statement which features that it possesses the revision control circuit which adjusts the speed which decreases electric potential the aforementioned time - on the basis of the output of the digital transmitter, by the aforementioned lamp circuit.
[claim5]
5. As for the aforementioned detector,
When output of the aforementioned comparator to which output of the aforementioned comparator to which among of the aforementioned plural comparators corresponds is input, is input transits, the plural 1st flip-flops which output transits and,
The operational circuit which does the logical operation which relates to the value of superior side of the aforementioned digital signal making use of the output of the aforementioned 1st flip-flop and,
When either among outputs of the aforementioned plural 1st flip-flops one output transits, taking in the output of the aforementioned operational circuit, the analog digital transmitter of the claim 3 statement which features that it possesses the plural 2nd flip-flops which you keep.
[claim6]
6. In the aforementioned comparator where 1st reference electric potential among plural aforementioned reference electric potential is input, it differs from the aforementioned 1st reference electric potential, changing 2nd reference electric potential among the aforementioned plural reference electric potential, into the aforementioned input electric potential, the switch in order to input and,
When the aforementioned 2nd reference electric potential which is input into the aforementioned comparator keeping decreasing at fixed speed by the aforementioned lamp circuit, the analog digital transmitter of the claim 5 statement which features that it possesses the revision control circuit which adjusts the speed which decreases electric potential the aforementioned time - on the basis of the output of the digital transmitter, by the aforementioned lamp circuit.
[claim7]
7. As for the aforementioned reference electric potential, in order to become high in fixed potential difference, either of the claim 1-6 which features that it is set in 1 sections the analog digital transmitter of statement.
[claim8]
8. Being the analog digital transmitter which converts the analog input signal which is input to the digital signal,
The track/truck and the hold circuit which sample the aforementioned analog input signal and,
The plural 1st comparators to which the input electric potential which responds to the aforementioned analog input signal which is sampled and the 1st reference electric potential which differs mutually are input, compare with the aforementioned input electric potential and the aforementioned 1st reference electric potential and,
The encoder which decides the value of specified bit number of superior side of the aforementioned digital signal on the basis of the output of the aforementioned plural 1st comparators and,
The remainder occurrence circuit which generates the remainder component which reduces the electric potential which corresponds to the value of superior side of the aforementioned digital signal which is decided from the aforementioned input electric potential and,
The 2nd comparator to which the aforementioned remainder component and 2nd reference electric potential is input, compares with the aforementioned remainder component and the aforementioned 2nd reference electric potential and,
The lamp circuit which decreases the aforementioned remainder component which is input into the aforementioned 2nd comparator at fixed speed and,
After starting to decrease the aforementioned remainder component by the aforementioned lamp circuit, until output of the aforementioned 2nd comparator transits, converting time to digital value, the time when it decides the value of remaining subordinate side of the aforementioned digital signal - the analog digital transmitter which features that it possesses the digital transmitter.
[claim9]
9. It is the discrete time comparator where the aforementioned 1st comparator, same period doing in the clock pulse, takes in input and compares,
As for the aforementioned 2nd comparator, the analog digital transmitter of the claim 8 statement which features that it is the continual time comparator which comparison of input usual is done.
[claim10]
10. As for the aforementioned remainder occurrence circuit,
The digital-analog converter which outputs the electric potential which corresponds to the value of superior side of the aforementioned digital signal which digital analog converts the output of the aforementioned encoder, is decided and,
The analog digital transmitter of the claim 9 statement which features that it possesses the subtracter which the electric potential which the aforementioned digital-analog converter outputs from the aforementioned input electric potential subtraction is done.
[claim11]
11. As for the aforementioned remainder occurrence circuit,
The analog digital transmitter of the claim 9 statement which features that it is the capacity type digital-analog converter which outputs the remainder component which reduces the electric potential to which output of the aforementioned analog input signal and the aforementioned encoder is input, corresponds to the value of superior side of the aforementioned digital signal from the input electric potential which responds to the aforementioned analog input signal.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • KAGOSHIMA UNIVERSITY
  • 発明者(英語)
  • OHHATA KENICHI
国際特許分類(IPC)
指定国 (WO201729984)
National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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