TOP > 外国特許検索 > Memory circuit

Memory circuit

外国特許コード F170009038
整理番号 AF15-01EP2
掲載日 2017年4月26日
出願国 欧州特許庁(EPO)
出願番号 16181451
公報番号 3107105
出願日 平成25年2月19日(2013.2.19)
公報発行日 平成28年12月21日(2016.12.21)
優先権データ
  • 特願2012-114988 (2012.5.18) JP
  • 2013EP-0791432 (2013.2.19) EP
発明の名称 (英語) Memory circuit
発明の概要(英語) (EP3107105)
A memory circuit includes a plurality of memory cells each including a bistable circuit configured to write data, and a nonvolatile element configured to store the data written in the bistable circuit in a nonvolatile manner and restore the data stored in a nonvolatile manner into the bistable circuit; and a control unit configured to determine whether the data in the bistable circuit is the same as data in the nonvolatile element in each memory cell of the plurality of memory cells.
特許請求の範囲(英語) [claim1]
1. A memory circuit comprising: a plurality of memory cells each including a bistable circuit configured to write data, and a nonvolatile element configured to store the data written in the bistable circuit in a nonvolatile manner and restore the data stored in a nonvolatile manner into the bistable circuit; and a control unit configured to determine whether the data in the bistable circuit is the same as data in the nonvolatile element in each memory cell of the plurality of memory cells, the control unit not storing the data written in the bistable circuit into the nonvolatile element when determining that the data in the bistable circuit is the same as the data in the nonvolatile element, the control unit storing the data in the bistable circuit into the nonvolatile element when determining that the data in the bistable circuit is not the same as the data in the nonvolatile element.
[claim2]
2. The memory circuit according to claim 1, wherein
the nonvolatile element stores the data in the bistable circuit by changing the resistance value thereof.
[claim3]
3. The memory circuit according to claim 1 or 2, wherein
the nonvolatile element has one end connected to a node in the bistable circuit and has the other end connected to a control line, and
the control unit determines whether the data in the bistable circuit is the same as the data in the nonvolatile element based on a voltage of the control line when there is data written in the bistable circuit.
[claim4]
4. The memory circuit according to claim 3, wherein
the bistable circuit includes a first node and a second node, the first node and the second node being complementary to each other, and
the nonvolatile element includes a first nonvolatile element and a second nonvolatile element, the first nonvolatile element having one end connected to the first node and the other end connected to the control line, the second nonvolatile element having one end connected to the second node and the other end connected to the control line.
[claim5]
5. The memory circuit according to claim 3, further comprising
a readout circuit configured to read out the data from the bistable circuit,
wherein the control unit determines whether the data in the bistable circuit is the same as the data in the nonvolatile element based on an output of the readout circuit and the voltage of the control line.
[claim6]
6. The memory circuit according to claim 5, wherein
the bistable circuit includes a first node and a second node, the first node and the second node being complementary to each other,
the control line includes a first control line and a second control line,
the nonvolatile element includes a first nonvolatile element and a second nonvolatile element, the first nonvolatile element having one end connected to the first node and the other end connected to the first control line, the second nonvolatile element having one end connected to the second node and the other end connected to the second control line, and
the control unit determines whether data in the first nonvolatile element and data in the second nonvolatile element contradict each other based on the output of the readout circuit and voltages of the first control line and the second control line.
[claim7]
7. The memory circuit according to any one of claims 1 through 6, wherein, when receiving a skip signal, the control unit does not determine whether the data in the bistable circuit is the same as the data in the nonvolatile element.
[claim8]
8. The memory circuit according to any one of claims 1 through 7, wherein the nonvolatile element is a ferromagnetic tunnel junction device.
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • YAMAMOTO SHUICHIRO
  • SHUTO YUSUKE
  • SUGAHARA SATOSHI
国際特許分類(IPC)
指定国 (EP3107105)
Contracting States: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
参考情報 (研究プロジェクト等) CREST Research of Innovative Material and Process for Creation of Next-generation Electronics Devices AREA
ライセンスをご希望の方、特許の内容に興味を持たれた方は、問合せボタンを押してください。

PAGE TOP

close
close
close
close
close
close