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TUNNEL FIELD EFFECT TRANSISTOR

外国特許コード F170009058
整理番号 K10103WO/S2015-2125-N0
掲載日 2017年4月26日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2016JP078393
国際公開番号 WO 2017057329
国際出願日 平成28年9月27日(2016.9.27)
国際公開日 平成29年4月6日(2017.4.6)
優先権データ
  • 特願2015-193196 (2015.9.30) JP
発明の名称 (英語) TUNNEL FIELD EFFECT TRANSISTOR
発明の概要(英語) The tunnel field effect transistor according to the present invention has: a channel; a source electrode connected directly or indirectly to one end of the channel; a drain electrode connected directly or indirectly to the other end of the channel; and a gate electrode for causing an electric field to act on the channel, generating a tunnel phenomenon at the source electrode-side joint part of the channel, and simultaneously generating a two-dimensional electron gas in the channel.
特許請求の範囲(英語) [claim1]
1. Channel and,
The source electrode which is connected to one end of the aforementioned channel directly or indirectly and,
Other than the aforementioned channel the drain electrode which is connected to the edge directly or indirectly and,
Operating electric field the aforementioned channel, as it makes tunnel phenomenon the joint of the aforementioned source electrode side of the aforementioned channel cause, the gate electrode which makes two dimensional electron gas the aforementioned channel cause simultaneously and,
It possesses, the tunnel field-effect transistor.
[claim2]
2. (111) The baseplate which consists of IV family semiconductor which possesses the surface, is doped to 1st electric conduction type and,
The insulator film which covered (111) the surface of the aforementioned baseplate, possesses the open part and,
The core multiple shell nano- wire which was arranged (111) on the surface of the aforementioned baseplate which is exposed on the aforementioned opening circles and on the aforementioned insulator film around the particular open part consists of the III-V family compound semiconductor and,
It was connected to the aforementioned baseplate, one side of the aforementioned source electrode and the aforementioned drain electrode and,
It was connected to the aforementioned core multiple shell nano- wire, another side of the aforementioned source electrode and the aforementioned drain electrode and,
The gate insulator film which is arranged on the side of the aforementioned core multiple shell nano- wire and,
The aforementioned gate electrode which was arranged on the aforementioned gate insulator film, operates electric field at least portion of the aforementioned core multiple shell nano- wire and,
Possessing,
As for the aforementioned core multiple shell nano- wire,
The 2nd territory which is doped to the 2nd electric conduction type which was connected to the 1st territory and the aforementioned 1st territory which are connected (111) to the surface of the aforementioned baseplate which is exposed on the aforementioned opening circles, differs from the aforementioned 1st electric conduction type is included, it consists of the III-V family compound semiconductor, the central nano- wire as the aforementioned channel and,
The barrier layer which consists of the III-V family compound semiconductor which is larger than the III-V family compound semiconductor where that band gap forms the aforementioned central nano- wire covers the side of the aforementioned central nano- wire and,
It is larger than the III-V family compound semiconductor where that band gap forms the aforementioned central nano- wire, it is smaller than the III-V family compound semiconductor which at the same time forms the aforementioned barrier layer, the irregularity dope layer which consists of the III-V family compound semiconductor of the aforementioned 2nd electric conduction type, covers the aforementioned barrier layer and,
The cap layer which consists of the III-V family compound semiconductor which is above the band gap of the III-V family compound semiconductor where that band gap forms the aforementioned central nano- wire, covers the aforementioned irregularity dope layer and,
Possessing,
The aforementioned 1st territory is the intrinsic semiconductor, or or we are doped by the aforementioned 2nd electric conduction type lower than impurity density of the aforementioned 2nd territory,
The aforementioned barrier layer and the aforementioned cap layer, respectively, are the intrinsic semiconductor, or or we are doped by the aforementioned 2nd electric conduction type lower than impurity density of the aforementioned irregularity dope layer,
Another side of the aforementioned source electrode and the drain electrode is connected by the aforementioned 2nd territory of the aforementioned central nano- wire,
The aforementioned gate electrode, operating electric field (111) with the connecting boundary of the surface and the aforementioned central nano- wire of the aforementioned baseplate and the aforementioned 1st territory of the aforementioned central nano- wire, as it makes tunnel phenomenon the aforementioned connecting boundary cause, makes two dimensional electron gas the aforementioned 1st territory cause simultaneously,
In claim 1 tunnel field-effect transistor of statement.
[claim3]
3. As the III-V family compound semiconductor which as the III-V family compound semiconductor where the aforementioned core multiple shell nano- wire is arranged between the aforementioned barrier layer and the aforementioned irregularity dope layer, forms the aforementioned irregularity dope layer is arranged between 1st spacer layer and the aforementioned irregularity dope layer and the aforementioned cap layer which consist of the III-V family compound semiconductor of the same constitution forms the aforementioned irregularity dope layer and the aforementioned 1st spacer layer the 2nd spacer layer which consists of the III-V family compound semiconductor of the same constitution furthermore possessing,
The band gap of the aforementioned 1st spacer layer and the aforementioned 2nd spacer layer is larger than the band gap of the III-V family compound semiconductor which forms the aforementioned central nano- wire, is smaller than the band gap of the III-V family compound semiconductor which at the same time forms the aforementioned barrier layer,
In claim 2 tunnel field-effect transistor of statement.
[claim4]
4. Impurity density of the aforementioned irregularity dope layer 10 (17) the -10 (21) is inside cm (- 3) range, claim 2 or in claim 3 the tunnel field-effect transistor of statement.
[claim5]
5. Either of the claim 1-4 the switching device which includes the tunnel field-effect transistor of statement in one section.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • HOKKAIDO UNIVERSITY
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • FUKUI TAKASHI
  • TOMIOKA KATSUHIRO
国際特許分類(IPC)
指定国 (WO201757329)
National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
参考情報 (研究プロジェクト等) PRESTO Phase Interfaces for Highly Efficient Energy Utilization AREA
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