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RADIATION-DAMAGE-COMPENSATION-CIRCUIT AND SOI-MOSFET

外国特許コード F170009097
整理番号 (S2015-1988-N66)
掲載日 2017年5月30日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2016JP079797
国際公開番号 WO 2017061544
国際出願日 平成28年10月6日(2016.10.6)
国際公開日 平成29年4月13日(2017.4.13)
優先権データ
  • 特願2015-199200 (2015.10.7) JP
  • 2016US-62312804 (2016.3.24) US
発明の名称 (英語) RADIATION-DAMAGE-COMPENSATION-CIRCUIT AND SOI-MOSFET
発明の概要(英語) The present invention provides a radiation-damage-compensation-circuit and a SOI-MOSFET that has high radiation resistance. The SOI-MOSFET has the radiation-damage-compensation-circuit to recover the characteristics of the SOI-MOSFET after X-ray irradiation.
特許請求の範囲(英語) [claim1]
1. [Rectified under Rule 91, 31.10.2016]
A radiation-damage-compensation-circuit fabricated with a SOI-MOSFET, comprising: a MOSFET-channel to detect a voltage threshold shift due to a radiation-induced positive charge in the BOX;
a path generating an external voltage under a control of the MOSFET-channel, applying a negative voltage corresponding to the voltage threshold shift to a current-source and applying a negative charge of the current-source to a buried p-well below the BOX.
[claim2]
2. A SOI-MOSFET, having the radiation-damage-compensation-circuit according to claim 1, connecting the MOSFET-channel, an external voltage-source, a silicon-diffusion-layer, the buried p-well and the BOX.
[claim3]
3. A SOI-MOSFET, having the radiation-damage-compensation-circuit according to claim 1, connecting the MOSFET-channel, a transistor, an external voltage-source, a via, the buried p-well and the BOX.
[claim4]
4. A SOI-MOSFET, having the radiation-damage-compensation-circuit according to claim 1, connecting a transistor, an external voltage-source, a via, the buried p-well and the BOX.
[claim5]
5. The SOI-MOSFET according to anyone of claims 2 to 4, having a buried n-well replaced with the buried p-well.
[claim6]
6. The SOI-MOSFET according to anyone of claims 2 to 4, having a partially or completely depletion.
[claim7]
7. The radiation-damage-compensation-circuit according to claim 1, for use to cancel a radiation-induced positive charge of a semiconductor-device requiring radiation resistance, said the radiation-damage-compensation-circuit being able to cancel the radiation-induced-positive-charge by applying an external voltage on the beneath of a transistor of the semiconductor-device.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION
  • 発明者(英語)
  • KURACHI IKUO
  • ARAI YASUO
  • YAMADA MIHO
国際特許分類(IPC)
指定国 (WO201761544)
National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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