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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE NEW

外国特許コード F170009154
整理番号 (S2016-0332-N0)
掲載日 2017年8月24日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2017JP002652
国際公開番号 WO 2017135132
国際出願日 平成29年1月26日(2017.1.26)
国際公開日 平成29年8月10日(2017.8.10)
優先権データ
  • 特願2016-018817 (2016.2.3) JP
発明の名称 (英語) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE NEW
発明の概要(英語) A semiconductor integrated circuit device in which inductive coupling between coils is improved and supply voltage drops in power supply wires are suppressed as a result of devising a power supply network. The semiconductor integrated circuit device is provided with a power supply network equipped with a first power supply wiring group that passes through the X direction and a second power supply wiring group that passes through the Y direction when viewing the interiors of all of the coils of a first coil array, which is formed in the same horizontal position in a multilayer wiring structure provided on a substrate and comprises a plurality of coils positioned at prescribed intervals, from the lamination direction of the multilayer wiring structure. A closed circuit that surrounds the sides of a coil is formed by at least part of the first power supply wiring group and at least part of the second power supply wiring group.
特許請求の範囲(英語) [claim1]
1. The 1st coil array which consists of the plural coils which are formed by the identical horizontal position in the multilayer interconnection structure which is provided on the baseplate are arranged at specified interval and,
The 1st power source wiring group which consists of the power source line pair of the power source line and the earthing conductor which pass X direction inside all aforementioned coils considered as the lamination direction of the aforementioned multilayer interconnection structure and considered as the lamination direction of the aforementioned multilayer interconnection structure the aforementioned X direction inside all aforementioned coils and has the 2nd power source wiring group which consists of the power source line and the earthing conductor the power source line pair the power source net which passes the Y direction which crosses possessing,
At least portion of the aforementioned 1st power source wiring group and at least portion of the aforementioned 2nd power source wiring group the semiconductor integrated circuit device which forms the closed circuit which surrounds around the aforementioned coil.
[claim2]
2. The aforementioned coil, in the claim 1 which is formed from the 2nd coil element which is parallel with the 1st coil element and the aforementioned 2nd power source wiring group which are parallel with the aforementioned 1st power source wiring group the semiconductor integrated circuit device of statement.
[claim3]
3. The aforementioned 1st coil element and the aforementioned 2nd coil element, are formed with wiring of the horizon which differs mutually,
The aforementioned 1st coil element and the aforementioned 2nd coil element alternately in the claim 2 which is connected by the beer the semiconductor integrated circuit device of statement.
[claim4]
4. The 2nd coil array which was formed vis-a-vis the aforementioned 1st coil array, as the aforementioned 1st coil array by the aforementioned multilayer interconnection structure which arranges at the same interval, the aforementioned 1st coil array and between specified
Every other just slipping, in order to be piled up, it arranges,
The aforementioned 1st power source wiring group X direction inside all aforementioned coils which form the aforementioned 2nd coil array considered as the lamination direction of the aforementioned multilayer interconnection structure is passed,
The aforementioned 2nd power source wiring group in the claim 3 which passes the aforementioned Y direction inside all aforementioned coils which form the aforementioned 2nd coil array considered as the lamination direction of the aforementioned multilayer interconnection structure the semiconductor integrated circuit device of statement.
[claim5]
5. The aforementioned 1st coil element and the aforementioned 2nd coil element, are formed with wiring of the same horizon,
In the claim 2 which is formed by wiring of the horizon where the aforementioned 1st power source wiring group and the aforementioned 2nd power source wiring group differ from the aforementioned 1st coil element and the aforementioned 2nd coil element the semiconductor integrated circuit device of statement.
[claim6]
6. In the claim 2 which is formed by the aforementioned multilayer interconnection structure which provide in the identical baseplate with the aforementioned 1st coil element and the aforementioned 2nd coil element and the aforementioned 1st power source wiring group and the aforementioned 2nd power source wiring group the semiconductor integrated circuit device of statement.
[claim7]
7. In the claim 2 which is formed by the aforementioned multilayer interconnection structure which is provided in the baseplate where differ from the aforementioned 1st coil element and the aforementioned 2nd coil element and the aforementioned 1st power source wiring group and the aforementioned 2nd power source wiring group mutually the semiconductor integrated circuit device of statement.
[claim8]
8. The aforementioned coil, vis-a-vis the aforementioned 1st power source wiring group in the claim 1 which is formed from the 4th coil element of slanted direction vis-a-vis the 3rd coil element and the aforementioned 2nd power source wiring group of slanted direction the semiconductor integrated circuit device of statement.
[claim9]
9. The aforementioned 3rd coil element and the aforementioned 4th coil element, are formed with wiring of the horizon which differs mutually,
The aforementioned 3rd coil element and the aforementioned 4th coil element alternately in the claim 8 which is connected by the beer the semiconductor integrated circuit device of statement.
[claim10]
10. The 2nd coil array which was formed vis-a-vis the aforementioned 1st coil array, as the aforementioned 1st coil array by the aforementioned multilayer interconnection structure which arranges at the same interval, in order just for the aforementioned 1st coil array and specified interval to slip and to be piled up it arranges,
The aforementioned 1st power source wiring group X direction inside all aforementioned coils which form the aforementioned 2nd coil array considered as the lamination direction of the aforementioned multilayer interconnection structure is passed,
The aforementioned 2nd power source wiring group in the claim 9 which passes the aforementioned Y direction inside all aforementioned coils which form the aforementioned 2nd coil array considered as the lamination direction of the aforementioned multilayer interconnection structure the semiconductor integrated circuit device of statement.
[claim11]
11. The aforementioned 3rd coil element and the aforementioned 4th coil element, are formed with wiring of the same horizon,
In the claim 8 which is formed by wiring of the horizon where the aforementioned 1st power source wiring group and the aforementioned 2nd power source wiring group differ from the aforementioned 3rd coil element and the aforementioned 4th coil element the semiconductor integrated circuit device of statement.
[claim12]
12. In the claim 8 which is formed by the aforementioned multilayer interconnection structure which provide in the identical baseplate with the aforementioned 3rd coil element and the aforementioned 4th coil element and the aforementioned 1st power source wiring group and the aforementioned 2nd power source wiring group the semiconductor integrated circuit device of statement.
[claim13]
13. In the claim 8 which is formed by the aforementioned multilayer interconnection structure which is provided in the baseplate where differ from the aforementioned 3rd coil element and the aforementioned 4th coil element and the aforementioned 1st power source wiring group and the aforementioned 2nd power source wiring group mutually the semiconductor integrated circuit device of statement.
[claim14]
14. The aforementioned 1st power source wiring group and the aforementioned 2nd power source wiring group, in the claim 1 which has shorted in inside all aforementioned coils the semiconductor integrated circuit device of statement.
[claim15]
15. The aforementioned 1st power source wiring group and the aforementioned 2nd power source wiring group, in the claim 1 which has shorted in the portion inside the aforementioned coil the semiconductor integrated circuit device of statement.
[claim16]
16. The aforementioned 1st power source wiring group and the aforementioned 2nd power source wiring group, in the claim 15 which has shorted at specified periodic interval in inside the aforementioned coil the semiconductor integrated circuit device of statement.
[claim17]
17. One end of the aforementioned 1st power source wiring group and one end of the aforementioned 2nd power source wiring group, in the claim 1 which is the open edge the semiconductor integrated circuit device of statement.
[claim18]
18. Inside each coil which forms the aforementioned 1st coil array and the aforementioned power source line pair plural passes inside each coil which forms the aforementioned 2nd coil array,
In the claim 4 where one end of the aforementioned 1st power source wiring group and one end of the aforementioned 2nd power source wiring group are the open edge the semiconductor integrated circuit device of statement.
[claim19]
19. Inside each coil which forms the aforementioned 1st coil array and the aforementioned power source line pair plural passes inside each coil which forms the aforementioned 2nd coil array,
In the claim 10 where one end of the aforementioned 1st power source wiring group and one end of the aforementioned 2nd power source wiring group are the open edge the semiconductor integrated circuit device of statement.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • KEIO UNIVERSITY
  • 発明者(英語)
  • KURODA TADAHIRO
国際特許分類(IPC)
指定国 (WO2017135132)
National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS KE KG KH KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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