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Memory circuit provided with bistable circuit and non-volatile element NEW_EN

Foreign code F170009249
File No. AF15-02EP2
Posted date Oct 5, 2017
Country EPO
Application number 17151073
Gazette No. 3174061
Date of filing Feb 19, 2013
Gazette Date May 31, 2017
Priority data
  • P2012-114989 (May 18, 2012) JP
  • 2013EP-0791129 (Feb 19, 2013) EP
Title Memory circuit provided with bistable circuit and non-volatile element NEW_EN
Abstract (EP3174061)
A memory circuit comprising: a bistable circuit (30) configured to write data; a nonvolatile element (MTJ1, MTJ2) configured to store data written in the bistable circuit (30) in a nonvolatile manner and restore data stored in a nonvolatile manner into the bistable circuit (30) by changing a resistance value with a current flowing between one end and the other end, the nonvolatile element (MTJ1, MTJ2) having the one end connected to a node (Q, QB) in the bistable circuit (30) and the other end connected to a control line (CTRL); an FET (m7, m8) having a source and a drain connected in series to the nonvolatile element (MTJ1, MTJ2) between the node (Q, QB) and the control line (CNTL); and a control unit (85) configured to make a voltage (SR) to be applied to a gate of the FET (m7, m8) during a period to restore data stored in the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner into the bistable circuit (30) lower than a supply voltage to be applied to the bistable circuit (30) during a period to write data into and read data from the bistable circuit (30) in a volatile manner.
Scope of claims [claim1]
1. A memory circuit comprising: a bistable circuit (30) configured to write data; a nonvolatile element (MTJ1, MTJ2) configured to store data written in the bistable circuit (30) in a nonvolatile manner and restore data stored in a nonvolatile manner into the bistable circuit (30) by changing a resistance value with a current flowing between one end and the other end, the nonvolatile element (MTJ1, MTJ2) having the one end connected to a node (Q, QB) in the bistable circuit (30) and the other end connected to a control line (CTRL); an FET (m7, m8) having a source and a drain connected in series to the nonvolatile element (MTJ1, MTJ2) between the node (Q, QB) and the control line (CNTL); and a control unit (85) configured to make a voltage (SR) to be applied to a gate of the FET (m7, m8) during a period to restore data stored in the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner into the bistable circuit (30) lower than a supply voltage to be applied to the bistable circuit (30) during a period to write data into and read data from the bistable circuit (30) in a volatile manner.
[claim2]
2. The memory circuit according to claim 1, wherein the control unit (85) makes the voltage (SR) to be applied to the gate during a period to store data written in the bistable circuit (30) into the nonvolatile element (MTJ1,MTJ2) in a nonvolatile manner lower than the supply voltage.
[claim3]
3. The memory circuit according to claim 1 or 2, wherein the control unit (85) makes the highest voltage to be applied to the control unit (85) during a period to store data written in the bistable circuit (30) into the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner lower than the supply voltage.
  • Applicant
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • Inventor
  • SHUTO YUSUKE
  • YAMAMOTO SHUICHIRO
  • SUGAHARA SATOSHI
IPC(International Patent Classification)
Specified countries (EP3174061)
Contracting States: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Reference ( R and D project ) CREST Research of Innovative Material and Process for Creation of Next-generation Electronics Devices AREA
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