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RECONFIGURABLE DELAY CIRCUIT, DELAY MONITOR CIRCUIT USING SAID DELAY CIRCUIT, VARIATION CORRECTION CIRCUIT, VARIATION MEASUREMENT METHOD, AND VARIATION CORRECTION METHOD 新技術説明会

Foreign code F150008480
File No. AF14-01WO
Posted date 2015年10月26日
Country 世界知的所有権機関(WIPO)
International application number 2014JP069976
International publication number WO 2015025682
Date of international filing 平成26年7月29日(2014.7.29)
Date of international publication 平成27年2月26日(2015.2.26)
Priority data
  • 特願2013-169965 (2013.8.19) JP
Title RECONFIGURABLE DELAY CIRCUIT, DELAY MONITOR CIRCUIT USING SAID DELAY CIRCUIT, VARIATION CORRECTION CIRCUIT, VARIATION MEASUREMENT METHOD, AND VARIATION CORRECTION METHOD 新技術説明会
Abstract A delay circuit (10) containing a first inverting circuit, which contains a pull-up circuit (2) and a pull-down circuit (3), and a second inverting circuit, which contains a pull-up circuit (4) and a pull-down circuit (5). The delay circuit also contains: a first pass transistor (6) connected in series to the pull-up circuit of the first inverting circuit between a power supply potential and an output node; a second pass transistor (7) connected in series to the pull-down circuit (2) of the first inverting circuit between a ground potential and the output node (Out); a third pass transistor (8) inserted in series between an input node (In) and the pull-up circuit of the second inverting circuit; and a fourth pass transistor (9) inserted in series between the input node and the pull-down circuit of the second inverting circuit. The delay characteristic of the delay circuit is changed by a combination of control signals (C1-C4) applied to the gates of the first - fourth pass transistors.
  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • Inventor
  • ONODERA HIDETOSHI
  • A K M MAHFUZUL ISLAM
IPC(International Patent Classification)
Reference ( R and D project ) CREST Fundamental Technologies for Dependable VLSI System AREA
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