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SEMICONDUCTOR INTEGRATED CIRCUIT AND DELAY MEASUREMENT CIRCUIT

Foreign code F160008877
File No. (S2015-0412-N0)
Posted date 2016年10月25日
Country 世界知的所有権機関(WIPO)
International application number 2016JP001185
International publication number WO 2016139958
Date of international filing 平成28年3月4日(2016.3.4)
Date of international publication 平成28年9月9日(2016.9.9)
Priority data
  • 特願2015-044113 (2015.3.5) JP
Title SEMICONDUCTOR INTEGRATED CIRCUIT AND DELAY MEASUREMENT CIRCUIT
Abstract A semiconductor integrated circuit according to one aspect of the present invention is provided with: a circuit unit to be measured provided with a plurality of connected flip-flop circuits; a clock generation circuit unit; and a delay measurement circuit unit which is provided with a NAND circuit, a plurality of NOT circuits connected in series with the NAND circuit, a counter circuit connected to terminals of the plurality of NOT circuits, and a scan chain circuit in which a plurality of selector circuits and a plurality of flip-flop circuits are connected. The NAND circuit is provided with at least two bias voltage input gates.
Outline of related art and contending technology BACKGROUND ART
The semiconductor integrated circuit, semiconductor material or insulating surface of the material or a semiconductor material with transistors of other circuit elements are generated, the function of the electronic circuit and is designed to have, a personal computer or a mobile phone or the like is used and, particularly in recent years, advances in miniaturization in the semiconductor integrated circuit technology and high-speed been prominently.
However, the high speed operation of the semiconductor integrated circuit, variations in machining the variation in the increase in capacitive coupling between the lines due to the variation of the propagation time of signals in the circuit results, how important is to reduce this variation has been a problem. That is a high-speed semiconductor integrated circuit in the circuit in order to manufacture a better yield the propagation time and determine the statistical variation, it is possible that improvement is necessary. The propagation time is longer than necessary as the method of confirming whether or not the delay measurement that.
Delay measurement is, a test signal is input and the response signal to be measured is referred to as a time to obtain, as a result, the measured time falls within a predetermined period of time to determine whether or not, whether or not a defective product can be determined.
However, the delay built in the semiconductor integrated circuit itself is also measured under the influence of a manufacturing variation, and due to the variation of the measurement itself. In this case, it is difficult to perform accurate delay measurement becomes.
Therefore, used in the known techniques, for example in the following Patent Document 1 and 2, delay measurement circuit to reduce the measurement error due to a variation in the disclosed technique.
  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • NATIONAL UNIVERSITY CORPORATION CHIBA UNIVERSITY
  • Inventor
  • NAMBA, Kazuteru
  • CUI, Ri
IPC(International Patent Classification)
Specified countries National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG

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