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Magnetoresistive element, tunnel barrier layer and method of manufacturing the magnetoresistive element UPDATE

Foreign code F110004849
File No. K02012WO
Posted date 2011年7月22日
Country 大韓民国
Application number 20067019694
Gazette No. 20060122970
Gazette No. 100867662
Date of filing 平成18年9月22日(2006.9.22)
Gazette Date 平成18年11月30日(2006.11.30)
Gazette Date 平成20年11月10日(2008.11.10)
International application number JP2005004720
International publication number WO2005088745
Date of international filing 平成18年9月22日(2006.9.22)
Date of international publication 平成17年9月22日(2005.9.22)
Priority data
  • 特願2004-071186 (2004.3.12) JP
  • 特願2004-313350 (2004.10.28) JP
Title Magnetoresistive element, tunnel barrier layer and method of manufacturing the magnetoresistive element UPDATE
Abstract A single crystal MgO(001) substrate (11) is prepared. An epitaxial Fe(001) lower electrode (first electrode) (17) having a thickness of 50 nm is deposited on an MgO(001) seed layer (15) at room temperature. In an ultrahigh vacuum (2x10(-8) Pa) state, annealing is preformed at 350.deg.C. An MgO(001) barrier layer (21) having a thickness of 2 nm is epitaxially deposited on the Fe(001) lower electrode (first electrode) (17) at room temperature by MgO electron beam vacuum deposition. An Fe(001) upper electrode (second electrode) (23) having a thickness of 10 nm is deposited on the MgO(001) barrier layer (21) at room temperature. Consecutively, a Co layer (21) having a thickness of 10 nm is deposited on the Fe(001) upper electrode (second electrode) (23). The Co layer (21) enhances the holding capability of the upper electrode (23) to realize an antiparallel magnetization arrangement. By microfabrication the above produced sample, Fe(001)/MgO(001)/Fe(001) TMR element is fabricated. Thus, the output voltage value of an MRAM can be increased.
(C) KIPO WIPO 2007
Outline of related art and contending technology BACKGROUND ART
Is MRAM (Magnetoresistive Random Access Memory), and are now widely used as a memory element is expected to take the place of DRAM capacity of the integrated memory device. In addition, the high speed nonvolatile memory device having the well (non field volatile memory) MRAM research and development is being carried out of the sample actually MRAM 4Mbit of which has been launched.
Fig. 8 is a, which is part of the most important MRAM tunnel magnetic resistance element (hereinafter, ' TMR element) is referred to as a) the structure of, the present invention and its operating principle. Fig. 8 (a) as shown in element TMR, made from an oxide of the tunnel barrier (hereinafter, 'barrier' is also referred to as a) on both sides of the second conductor layer composed of a ferromagnetic metal 1, 2 of the first of the two electrodes is sandwiched between a tunnel junction structure can be intended. As the tunnel barrier layer, an amorphous layer of the utilized Al field O (see non patent document 1). Fig. 8 (a) as shown, the first ferromagnetic electrode and the second ferromagnetic electrode 1 with 2 parallel to the direction of magnetization in the case of parallel magnetization, the tunnel structure at the interface of a normal tube electrical resistance of the element becomes small. On the other hand, Fig. 8 (b) as shown in the first ferromagnetic electrode 1 with the electrode 2 and the second ferromagnetic is parallel to the direction of magnetization in the case of antiparallel magnetization, the direction normal to the interface of the tunnel structure in an increase in electrical resistance of the element below.
This resistance value, the general condition because it does not change in, 1 or 0 is""""information in resistance of the resistance value can be stored according to the present invention. The parallel magnetization and antiparallel magnetization arrangement is stored in the nonvolatile memory (a non field volatile fashion) therefore, the nonvolatile memory can be used as base components.
Fig. 9 is a, diagram illustrating an example of a basic structure of MRAM and, Fig. 9 (a) is a perspective view of the MRAM, Fig. 9 (b) is a structural view showing a schematic circuit diagram, Fig. 9 (c) is a, sectional view of the structure.
Fig. 9 (a) as shown, the word line and bit line in the MRAM WL BL arranged as the intersection, the intersection cell MRAM disposed therein. (B) in Fig. 9 as shown, word lines and bit lines are placed at an intersection of a cell is MRAM, TMR element, the element is connected in series TMR MOSFET for possession, that performs a function as a load resistance of the resistance value by TMR MOSFET read out by the, and the storage information can be read. On the other hand, the rewriting of information, for example, by the application of a magnetic field to the element TMR can be performed. Fig. 9 (c) as shown, the MRAM memory cell, P type source region formed in the substrate 101 Si and drain regions 103 and 105, and a channel region that is defined with respect to a gate electrode formed on the owner MOSFET 100 and 111, 117 TMR in possession of a device of the present invention. A source region 105(GND) is the ground, a drain, connected to the bit line via BL TMR element of the present invention. The gate electrode 111 with respect to the word line WL as shown in the drawing area that is not connected in the present invention.
As described above is a nonvolatile memory MRAM, 1 MOSFET 100 and 117 of element 1 by two memory cell TMR form because it can be, and is suitable for the integration of the memory element can be.
Non Patent literature 1: D. Wang, et al.: Science 294 (2001) 1488.
Scope of claims [claim1]
1. AMEND STATUS: Delete

[claim2]
2. AMEND STATUS: delete

[claim3]
3. A tunnel barrier layer; 1 wherein said tunnel barrier layer formed on the first surface having a structure or BCC Fe Fe alloy single (001) crystal layer or (001) a crystal plane is preferentially oriented polycrystalline layer a second ferromagnetic layer consisting of 1; 2 wherein said tunnel barrier layer formed on the first surface having a structure or BCC Fe Fe alloy single (001) crystal layer or (001) a crystal plane is preferentially oriented polycrystalline layer comprises a first ferromagnetic layer 2; comprising equipped with a magnetic tunnel junction structure, wherein the tunnel barrier layer, a polycrystalline or (001) monocrystalline MgOx (001) MgOx crystal plane is preferentially oriented (1 0 x<<) which is formed by a layer and the magnetoresistive element, and the lower part of the conduction band of the tunnel barrier layer, 2 or 1 wherein at least either one of the first ferromagnetic layer located between the discrete values of Fermi (height of tunnel barrier) of the range of 0.10-0.85 eV to the magnetoresistive element.

[claim4]
4. A tunnel barrier layer; 1 wherein said tunnel barrier layer formed on the first surface having a second ferromagnetic layer 1 BCC structure; 2 wherein said tunnel barrier layer structure formed on the first surface and a first ferromagnetic layer 2 BCC; magnetic tunnel junction structure comprising a tail, wherein the tunnel barrier layer is single crystal MgOX (001) MgO crystal plane is preferentially oriented or (001) polycrystallineX(0<X<1) formed by a layer of the magnetoresistive element and, wherein the tunnel barrier layer and the lower part of the conduction band, 2 or 1 at least one of the first ferromagnetic layer located between the discrete hand Fermi value (height of tunnel barrier) is in the range of 0.10-0.85 eV of the magnetoresistive elements.

[claim5]
5. Method according to claim 3, wherein said discontinuous value is 0.2 ∼ 0. 5eV the range of the magnetoresistive element.

[claim6]
6. Method according to claim 4, wherein said discontinuous value is in the range of 0.2 ∼ 0.5 eV to the magnetoresistive element.

[claim7]
7. 1 the two transistor; as the load of the transistor 3 can be rewritten according to any one of the claims 6 the magnetoresistive element; configured memory device comprising.

[claim8]
8. 1 Preparing a substrate with the first step;
1Fe the structure on the substrate having a first alloy or BCC Fe crystal plane is preferentially oriented single (001) crystal layer (001) or the polycrystalline layer is deposited as a first step 2;
1Fe the structure of the alloy Fe BCC or single (001) crystal layer on the, single crystal or (001) polycrystalline MgOx MgOx (001) crystal plane is preferentially oriented (1 0 x<<) tunnel barrier layer consisting of vacuum deposition in a first ball state step 3;
2Fe the tunnel barrier structure having a first alloy Fe BCC or single (001) crystal layer (001) or of a crystal plane is preferentially oriented polycrystalline layer to form the 4 step; comprising a magnetoresistive element of said method.

[claim9]
9. Crystal plane is preferentially oriented single crystal or (001) polycrystalline MgOx MgOx (001) (1 0 x<<) preparing a substrate made of a step 1;
1Fe Or over said substrate having a first alloy Fe BCC single (001) layer structure or a (001) crystal plane is preferentially oriented and crystalline layer, subsequently, annealing for crystallization is carried out with the step 2;
1Fe the structure of (001) the alloy or BCC Fe MgOx (001) layer on the polycrystalline or (001) single crystal plane is preferentially oriented in (1 0 x<<) MgOx tunnel barrier layer comprising a second vacuum chamber at 3 ball state step;
2Fe the first tunnel barrier structure Fe BCC based alloy or a single (001) layer or (001) a crystal plane is preferentially oriented polycrystalline layer to form the 4 step; characterized in that it comprises a method of manufacturing a magnetoresistive element.

[claim10]
10. Method according to claim 8 or 9, wherein between 2 and 1 the first processing step, the crystal plane is preferentially oriented polycrystalline or (001) monocrystalline MgOx (001) MgOx (1 0 x<<) growing a seed layer consisting of the further comprising a step of a method of manufacturing a magnetoresistance element.

[claim11]
11. Method according to claim 8 or 9, or (001) a single crystal plane is preferentially oriented polycrystalline MgOx MgOx (001) (1 0 x<<) step of forming the tunnel barrier layer consisting of in, to adjust the values of X MgOx further comprising a step of the method of manufacturing a magnetoresistance element.

[claim12]
12. Preparing a substrate;
1Fe the substrate structure over the first alloy or BCC Fe crystal plane is preferentially oriented single (001) crystal layer (001) or a polycrystalline layer and the step of depositing;
1Fe the structure of (001) the alloy or BCC Fe MgO (amorphous) is made of an amorphous layer onXlayer and forming, by annealing the amorphous MgOXMgOx (001) crystallizing the layer of single crystal or (001) polycrystalline crystal plane is preferentially oriented (1 0 x<<) MgOx tunnel barrier layer comprising the steps of;
2Fe the tunnel barrier structure having a first alloy or BCC Fe crystal plane is preferentially oriented single (001) crystal layer (001) or a polycrystalline conductive layer; comprising a magnetoresistance element according to said method.

[claim13]
13. Method according to claim 12, wherein the amorphous MgOXlayer by sputtering, the X value of the adjusted target MgOx using the depositing method of manufacturing a magnetoresistance element.

[claim14]
14. Method according to claim 12, (amorphous) MgO the amorphousXduring forming, the step of adjusting the value of X MgOx further comprises a method of manufacturing magnetoresistance element.

[claim15]
15. A tunnel barrier layer; 1 wherein said tunnel barrier layer formed on the first surface is made of an amorphous magnetic alloy (amorphous) a first ferromagnetic layer 1, wherein the tunnel barrier layer 2 formed on the first surface is made of an amorphous magnetic alloy (amorphous) a first ferromagnetic layer 2; magnetic tunnel junction structure comprising a tail, wherein the tunnel barrier layer crystal plane is preferentially oriented, (001) (1 x 0<<) polycrystalline MgOx layer formed by the magnetoresistive element.

[claim16]
16. Method according to claim 15, a lower end of the conduction band of said tunnel barrier layer, wherein at least either one of 1 or 2 located between the ferromagnetic layer of the discrete values of Fermi (height of tunnel barrier) is in a range 0.10-0.85 eV of the magnetoresistive elements.

[claim17]
17. AMEND STATUS: Delete

[claim18]
18. Method according to claim 16, wherein said discontinuous value is 0.2 ∼ 0. 5eV the range of the magnetoresistive element.

[claim19]
19. AMEND STATUS: Delete

[claim20]
20. 1 the two transistor; writing transistor as a load of the first 15 device, any one of claims 16 18 or the second based on the first magnetoresistive element; memory element comprising.

[claim21]
21. Preparing a substrate;
(Amorphous) onto the substrate is made of an amorphous magnetic alloy layer and depositing the second ferromagnetic body 1;
1 the first ferromagnetic layer on the amorphous MgO layer and forming, by annealing the amorphous MgO MgOx (001) crystallizing the layer of the single crystal or (001) polycrystalline crystal plane is preferentially oriented (1 0 x<<) MgOx made comprises a step of forming the tunnel barrier layer;
Said tunnel barrier is made of an amorphous magnetic alloy (amorphous) a first step of depositing a ferromagnetic layer 2; comprising a magnetoresistance element according to said method.

[claim22]
22. Method according to claim 21, wherein the single crystal plane is preferentially oriented or (001) polycrystalline MgOx MgOx (001) (1 0 x<<) tunnel barrier layer comprising a step of forming, by sputtering a target of the X value is adjusted MgOx of depositing comprises using the method of manufacturing a magnetoresistance element.

[claim23]
23. A tunnel barrier layer; first tunnel barrier layer 1 formed on a surface of a first ferromagnetic layer 1; 2 wherein said tunnel barrier layer 2 formed on the second side of the first ferromagnetic layer; equipped with a magnetic tunnel junction structure having,
Wherein the tunnel barrier layer, (001) the crystal plane is preferentially oriented polycrystalline MgOX (0<X<1) layer being formed on,
Wherein the tunnel barrier layer and the lower part of the conduction band, at least one of the first ferromagnetic layer 1 or 2 between the fermi level of the discrete values within a range 0.10-0.85 eV (height of tunnel barrier) to the magnetoresistive element.

[claim24]
24. Method according to claim 23, wherein said discontinuous value is in a range 0.2-0.5 eV magnetoresistive element.

[claim25]
25. AMEND STATUS: Delete

[claim26]
26. A ferromagnetic layer consisting of an amorphous magnetic alloy formed on the crystal plane is preferentially oriented, (001) polycrystalline MgOX (0<X<1) tunnel barrier layer and composed of,
Wherein the tunnel barrier layer and the lower part of the conduction band, wherein the ferromagnetic layer with a fermi level of 0.10-0.85 eV (the height of the tunnel barrier layer) discrete values in the range of the said tunnel barrier layer.

[claim27]
27. Method according to claim 26, wherein said discontinuous value is in a range 0.2-0.5 eV of the tunnel barrier layer.

[claim28]
28. AMEND STATUS: Delete

[claim29]
29. (001) the crystal plane is preferentially oriented polycrystalline MgOX (0<X<1) tunnel barrier layer consisting of, in a range 0.2-0.5 eV of the tunnel barrier height of the tunnel barrier layer.

[claim30]
30. AMEND STATUS: Delete
  • Applicant
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • Inventor
  • YUASA SHINJI
IPC(International Patent Classification)
Reference ( R and D project ) PRESTO Nanostructure and Material Property AREA
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