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Thin film transistor and method for manufacturing thin film transistor

Foreign code F170009220
File No. E086P50US1
Posted date 2017年9月13日
Country アメリカ合衆国
Application number 201615352560
Gazette No. 20170133517
Date of filing 平成28年11月15日(2016.11.15)
Gazette Date 平成29年5月11日(2017.5.11)
International application number JP2013057621
International publication number WO2013141197
Date of international filing 平成25年3月18日(2013.3.18)
Date of international publication 平成25年9月26日(2013.9.26)
Priority data
  • 特願2012-068133 (2012.3.23) JP
  • 2013JP57621 (2013.3.18) WO
  • 201414386811 (2014.9.21) US
Title Thin film transistor and method for manufacturing thin film transistor
Abstract A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate electrode 20 and the channel 44 and made of oxide (possibly containing inevitable impurities, this applies to oxide hereinafter) containing lanthanum and zirconium. The channel 44 is made of channel oxide including first oxide containing indium, zinc, and zirconium (Zr) having an atomic ratio of 0.015 or more and 0.075 or less relative to indium assumed to be 1 in atomic ratio, second oxide containing indium and zirconium (Zr) having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio, or third oxide containing indium and lanthanum having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio.
Outline of related art and contending technology BACKGROUND ART
Conventionally disclosed is a thin film transistor that includes a gate insulating layer made of a ferroelectric material (e.g. BLT (Bi4-XLaXTi3O12) or PZT (Pb(ZrX, Ti1-X)O3)) in order to enable rapid switching at a low drive voltage. Meanwhile, also disclosed in order to increase carrier density is a thin film transistor that includes a channel made of an oxide conductive material (e.g. indium tin oxide (ITO), zinc oxide (ZnO), or LSCO (LaXSr1-XCuO4)) (Patent Document 1).
In a method for manufacturing the thin film transistor mentioned above, a gate electrode of laminated films made of Ti and Pt is formed in accordance with an electron-beam evaporation technique. The gate insulating layer made of BLT or PZT is formed on the gate electrode in accordance with a sol-gel technique. The channel made of ITO is further formed on the gate insulating layer in accordance with a RF-sputtering technique. Subsequently formed on the channel are Ti and Pt serving as a source electrode and a drain electrode in accordance with an electron-beam evaporation technique. An element region is then isolated from a different element region in accordance with a RIE technique and a wet etching technique (using a mixed solution of HF and HCI) (Patent Document 1). The inventors of this application have studied selection and combination of oxide that appropriately exhibits functions as a thin film transistor (Patent Document 2).
Scope of claims [claim1]

1-14. (canceled)

[claim2]
15. A thin film transistor comprising a gate electrode, a channel, and a gate insulating layer provided between the gate electrode and the channel and made of oxide (possibly including inevitable impurities) containing lanthanum (La) and zirconium (Zr); wherein
the channel is made of
fourth oxide (possibly including inevitable impurities) containing indium (In), zinc (Zn), and tin (Sn), or fifth oxide (possibly including inevitable impurities) containing indium (In) and zinc (Zn).

[claim3]
16. The thin film transistor according to claim 15, wherein
the zinc (Zn) in the fourth oxide has atomicity of 0.15 or more and 0.75 or less relative to atomicity of the indium assumed to be 1, and
the tin (Sn) has atomicity of 0.5 or more and 2 or less relative to atomicity of the indium assumed to be 1.
17-22. (canceled)
  • Inventor, and Inventor/Applicant
  • SHIMODA Tatsuya
  • INOUE Satoshi
  • PHAN Tue Trong
  • MIYASAKO Takaaki
  • Li Jinwang
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
IPC(International Patent Classification)
Reference ( R and D project ) ERATO SHIMODA Nano-Liquid Process AREA
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