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MULTI-STAGE LOGIC RECONFIGURATION DEVICE AND RECONFIGURATION METHOD, LOGIC CIRCUIT CORRECTION DEVICE, AND RECONFIGURABLE MULTI-STAGE LOGIC CIRCUIT 実績あり

Foreign code F110002468
File No. 5034PCT
Posted date 2011年3月8日
Country 世界知的所有権機関(WIPO)
International application number 2007JP054100
International publication number WO 2007/113964
Date of international filing 平成19年3月2日(2007.3.2)
Date of international publication 平成19年10月11日(2007.10.11)
Priority data
  • 特願2006-101107 (2006.3.31) JP
Title MULTI-STAGE LOGIC RECONFIGURATION DEVICE AND RECONFIGURATION METHOD, LOGIC CIRCUIT CORRECTION DEVICE, AND RECONFIGURABLE MULTI-STAGE LOGIC CIRCUIT 実績あり
Abstract Provided is a multi-stage logic circuit reconfiguration device capable of easily reconfiguring a multi-stage logic circuit which can perform logic modification and requires a small mounting area and a low power consumption. For example, when reconfiguring a multi-stage logic circuit accompanying a logic modification for deleting an output vector F(b) of a target logic function F(X) for an input vector (b), uncorrected pq elements are successively selected starting with the pq element (EG) nearest to the output side. Here, among the pq elements of input side as compared to the pq elements which have been selected previously, those elements having an output value for the input vector (b) equal to the output value for the input variable (X) other than the input vector (b) are all considered to have been corrected and not selected. The output value for the selected input vector (b) is rewritten into an invalid value.
  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • KYUSHU INSTITUTE OF TECHNOLOGY
  • Inventor
  • SASAO, Tsutomu
IPC(International Patent Classification)
Specified countries AE(UTILITY MODEL),AG,AL(UTILITY MODEL),AM(PROVISIONAL PATENT)(UTILITY MODEL),AT(UTILITY MODEL),AU,AZ(UTILITY MODEL),BA,BB,BG(UTILITY MODEL),BR(UTILITY MODEL),BW,BY(UTILITY MODEL),BZ(UTILITY MODEL),CA,CH,CN(UTILITY MODEL),CO(UTILITY MODEL),CR(UTILITY MODEL),CU(INVENTOR'S CERTIFICATE),CZ(UTILITY MODEL),DE(UTILITY MODEL),DK(UTILITY MODEL),DM,DZ,EC(UTILITY MODEL),EE(UTILITY MODEL),EG(UTILITY MODEL),ES(UTILITY MODEL),FI(UTILITY MODEL),GB,GD,GE(UTILITY MODEL),GH,GM,GT,HN,HR(CONSENSUAL PATENT),HU(UTILITY MODEL),ID,IL,IN,IS,JP(UTILITY MODEL),KE(UTILITY MODEL),KG(UTILITY MODEL),KM,KN,KP(INVENTOR'S CERTIFICATE)(UTILITY MODEL),KR(UTILITY MODEL),KZ(PROVISIONAL PATENT)(UTILITY MODEL),LA,LC,LK,LR,LS(UTILITY MODEL),LT,LU,LY,MA,MD(UTILITY MODEL),MG,MK,MN,MW,MX(UTILITY MODEL),MY(UTILITY-INNOVATION),MZ(UTILITY MODEL),NA,NG,NI(UTILITY MODEL),NO,NZ,OM,PG,PH(UTILITY MODEL),PL(UTILITY MODEL),PT(UTILITY MODEL),RO,RS(PETTY PATENT),RU(UTILITY MODEL),SC,SD,SE,SG,SK(UTILITY MODEL),SL(UTILITY MODEL),SM,SV,SY,TJ(UTILITY MODEL),TM(PROVISIONAL PATENT),TN,TR(UTILITY MODEL),TT(UTILITY CERTIFICATE),TZ,UA(UTILITY MODEL),UG(UTILITY CERTIFICATE),US,UZ(UTILITY MODEL),VC(UTILITY CERTIFICATE),VN,ZA,ZM,ZW,EP(AT,BE,BG,CH,CY,CZ,DE,DK,EE,ES,FI,FR,GB,GR,HU,IE,IS,IT,LT,LU,LV,MC,MT,NL,PL,PT,RO,SE,SI,SK,TR),OA(BF(UTILITY MODEL),BJ(UTILITY MODEL),CF(UTILITY MODEL),CG(UTILITY MODEL),CI(UTILITY MODEL),CM(UTILITY MODEL),GA(UTILITY MODEL),GN(UTILITY MODEL),GQ(UTILITY MODEL),GW(UTILITY MODEL),ML(UTILITY MODEL),MR(UTILITY MODEL),NE(UTILITY MODEL),SN(UTILITY MODEL),TD(UTILITY MODEL),TG(UTILITY MODEL)),AP(BW,GH,GM,KE,LS,MW,MZ,NA,SD,SL,SZ,TZ,UG,ZM,ZW),EA(AM,AZ,BY,KG,KZ,MD,RU,TJ,TM)
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