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D-TYPE FLIP-FLOP CIRCUIT

外国特許コード F200010149
整理番号 (S2018-0693-N0)
掲載日 2020年6月2日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2019JP021613
国際公開番号 WO 2019235363
国際出願日 令和元年5月30日(2019.5.30)
国際公開日 令和元年12月12日(2019.12.12)
優先権データ
  • 特願2018-106763 (2018.6.4) JP
発明の名称 (英語) D-TYPE FLIP-FLOP CIRCUIT
発明の概要(英語) A D-type flip-flop circuit 1 has a configuration in which a pMOS transistor p8 and an nMOS transistor n8 are added to pMOS transistors p1-p7, p11-p15 and nMOS transistors n1-n7, n11-n15 which are provided to a typical D-type flip-flop circuit.
従来技術、競合技術の概要(英語) BACKGROUND ART
Integrated circuit (LSI) is, the miniaturization and the high-density integration and high performance, it also increases the performance of a computer by the progress of miniaturization has been in the walk cycle. However, with miniaturization of the processes, represented by a soft error transient is increased. Are exposed to harsh cosmic ray soft error is used in the space of the integrated circuit is a problem, in recent years and the ground is necessary to take measures of a soft error may have been. The soft error is, the radiation passes through the integrated circuit, or by the collision of electron-hole pairs are generated, the stored value of the temporary memory to the logic value of the flip-flop can be inverted in error.
Fig. 14 is, the principle of the generation of soft errors. Neutrons collide with Si atoms of the substrate 2 by a secondary ion is generated. Alpha rays or heavy ions, the ion beam 2 passes through the vicinity of the diffusion layer, the drift electric field of the depletion layer and the diffusion in the gas diffusion layer by an electron or a hole is collected. This electron or hole and the drain potential of the output is inverted.
As shown in Fig. 15 and Fig. 16, a transistor constituting a latch circuit and the radiation passes, the charge generated by ionization by radiation, high output (high level) of the transistor (low level) the row is temporarily inverted. The output of the transistor stable in an inverted state, the malfunction of the circuit.
Therefore, high reliability is necessary for the medical equipment, aircraft and automotive, or a server or a large circuit scale for the integrated circuits used for a supercomputer or the like, in particular, a required measure against soft errors. In addition, in recent years due to the miniaturization of the integrated circuit and integrated by a low power supply potential, and the manifestation of the effect of soft errors. From which the soft error measures for the integrated circuit is essential.
As a countermeasure against soft errors, the method measures at the circuit level, device level circuit would be used as a measure for the method.
As a countermeasure against the circuit level, the storage element (flip-flop circuit) for multiplexing structure can be exemplified.
Fig. 17 is, the flip-flop (FF) circuit and the triple, each of the flip-flop circuit is connected to the output of the majority circuit shown TMRFF(Triple Modular Redundancy Flip Flop). TMRFF is, one of the two flip-flop circuits 3, 1 only one row high by a soft output may be reversed, the correct output value of the output 2 of the other one if maintained, the majority circuit, the correct signal is output by a majority decision. In this way, by multiplexing the flip-flop circuit, soft error resistance is high. However, the flip-flop circuit for a triplex, compared to a general D-type flip-flop TMRFF, the circuit area, delay time and power consumption are respectively, 5.2 times, 1.5 times and increases to about 3.2 times.
In this way, in the measures at the level of the circuit, and is high in reliability, area, delay time and power consumption is a problem that the overhead is large.
On the other hand, as a countermeasure against the device level, the transistor a silicon substrate (silicon surface) of the insulator layer is provided between, can be exemplified by a so-called FD-SOI(Fully Depleted Silicon On Insulator) structure.
As shown in Fig. 18, FD-SOI structure, the silicon substrate and the transistor is referred to as BOX (Buried OXide) between the insulator layer is provided. As BOX layer, SiO2 is used mainly. According to this, the drain to the collection of the photogenerated carriers can be suppressed for the BOX layer, as compared with the soft error resistance is 50-100 times the bulk structure can be improved to the extent.
However, the FD-SOI structure, the problem of soft errors caused by parasitic bipolar effect. Specifically, as shown in Fig. 19, in the case of the nMOS transistor is the parasitic bipolar transistor due to the positive holes remaining in the substrate becomes ON, the charge collected to the drain, the holding value is inverted.
Therefore, sufficient for the countermeasure against soft errors, FD-SOI structure and a countermeasure device level, circuit level is necessary to combine measures.
Such as one of the countermeasures, C element to the non-multiplexed has been proposed (Non-Patent Document 1). As shown in Fig. 20, the elements C, between the power supply potential and the reference potential p101 connected to the pMOS transistor, the transistor pMOS p102, nMOS transistor and pMOS transistor n101 comprises a p102, nMOS p102 and pMOS transistor In2 is input to the transistor n101, inverter IN103, IN104 is composed of nMOS transistor n102 pMOS transistor p101 and by a delay circuit In1 is delayed with respect to the input. Therefore, the inverter IN105 is instantaneously generated due to soft error in the pulse, the transistor pMOS p102 pMOS transistor p101 and, as well as, nMOS transistor n101 and nMOS transistor n102 is not switched at the same time, the output OUT does not change.
In addition, as shown in Fig. 21, only nMOS transistor n101 ON by the parasitic bipolar effect, if the nMOS transistor n102 is OFF, the output OUT does not change. C FD-SOI structure such as a non-multiplexed by using the element in order to prevent, the soft error resistance can be improved.
In non-patent document 2, using the C element is not in a multiplexed D flip-flop circuit is subjected to a countermeasure (Guard-Gate Flip Flop) has been proposed. Fig. 22 is, in general a circuit diagram of the D-type flip-flop circuit 10, Fig. 23 is, as disclosed in Non-Patent Document 2 is a circuit diagram of a D-type flip-flop circuit 20 is.
D-type flip-flop circuit 10 is and, TGFF(Transmission Gate Flip Flop), as shown in Fig. 22, and master latch LA11, the transmission gate TG and, and the slave latch LA12, and the tri-state inverter T3, and inverter IN10, the clock signal generating circuit CL is provided. The master latch LA11, p1 and nMOS transistor n1 pMOS transistor IN1 and the inverter INV, the transistor pMOS p2, pMOS transistor p3, nMOS n2 and nMOS transistor T11 and a tri-state inverter having a transistor n3 and, when CLK=1 holds the value in the master latch LA11. The slave latch LA12, pMOS transistor p5 and nMOS transistor IN2 and the inverter INV n5, the transistor pMOS p6, pMOS transistor p7, nMOS n6 and nMOS transistor T12 and a tri-state inverter having a transistor n7 and, when CLK=0 in the slave latch LA12 holds the value.
D-type flip-flop circuit 10 is, any one of the MOS constituting the inverter IN1 the output of the tri-state inverters or any of the MOS T11 constituting the output of the inverted by a soft error, the stored value of the master latch LA11 changes. Similarly, any one of the MOS constituting the inverter IN2 the output of the tri-state inverters or any of the MOS T12 constituting the output of the inverted by a soft error, the stored value of the slave latch LA12 changes.
Therefore, D-type flip-flop circuit 20 is shown in Fig. 23, in the general D-type flip-flop circuit 10, inverter IN1 and inverter IN2 are replaced with C C element C1 and element C2, further, to the C element C1 to one input of the inverter IN21, is provided a delay circuit having IN22, C2 to one input of the C element IN23 to the inverter, a delay circuit having a configuration IN24 is provided. In this way, the D-type flip-flop circuit 20, a typical D-type flip-flop circuit 10 to the non-multiplexed to the element C by performing a countermeasure, and the resistance to soft errors.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • KYOTO INSTITUTE OF TECHNOLOGY
  • 発明者(英語)
  • KOBAYASHI KAZUTOSHI
  • FURUTA JUN
  • YAMADA KODAI
国際特許分類(IPC)
指定国 National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JO JP KE KG KH KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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