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Magnetic tunnel junction device NEW

外国特許コード F200010267
整理番号 K02012US9
掲載日 2020年11月9日
出願国 アメリカ合衆国
出願番号 202016862598
公報番号 20200259077
出願日 令和2年4月30日(2020.4.30)
公報発行日 令和2年8月13日(2020.8.13)
国際出願番号 JP2005004720
国際公開番号 WO2005088745
国際出願日 平成17年3月10日(2005.3.10)
国際公開日 平成17年9月22日(2005.9.22)
優先権データ
  • 特願2004-071186 (2004.3.12) JP
  • 特願2004-313350 (2004.10.28) JP
  • 200510591947 (2005.3.10) US
  • 2005JP04720 (2005.3.10) WO
  • 201012923643 (2010.9.30) US
  • 201213400340 (2012.2.20) US
  • 201313767290 (2013.2.14) US
  • 201514837558 (2015.8.27) US
  • 201715428842 (2017.2.9) US
  • 201916443875 (2019.6.18) US
発明の名称 (英語) Magnetic tunnel junction device NEW
発明の概要(英語) The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment.
従来技術、競合技術の概要(英語) BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a magnetic tunnel junction device and a method of manufacturing the same, particularly to a magnetic tunnel junction device with a high magnetoresistance and a method of manufacturing the same.
Description of Related Art
Magnetoresistive random access memories (MRAMs) refer to a large-scale integrated memory circuit that is expected to replace the currently widely used DRAM memories. Research and development of MRAM devices, which are fast and non-volatile memory devices, are being extensively carried out, and sample products of a 4 Mbit MRAM have actually been delivered.
FIGS. 8(A) and 8(B) show the structure and operation principle of a magnetic tunnel junction device (to be hereafter referred to as a “MTJ device”), which is the most important part of the MRAM. As shown in FIG. 8(A), a MTJ device comprises a tunnelling junction structure in which a tunnel barrier (to be hereafter also referred to as a “barrier layer”) made of an oxide is sandwiched between a first and a second electrode made of a ferromagnetic metal. The tunnel barrier layer comprises an amorphous Al—O layer (see Non-Patent Document 1). As shown in FIG. 8(A), in the case of parallel magnetization alignment where the directions of magnetizations of the first and second ferromagnetic electrodes are aligned parallel, the electric resistance of the device with respect to the direction normal to the interfaces of the tunneling junction structure decreases. On the other hand, in the case of antiparallel magnetization alignment where the directions of magnetizations of the first and second ferromagnetic electrodes are aligned antiparallel as shown in FIG. 8(B), the electric resistance with respect to the direction normal to the interfaces of the tunneling junction structure increases. The resistance value does not change in a general state, so that information “1” or “0” can be stored depending on whether the resistance value is high or not. Since the parallel and antiparallel magnetization alignments can be stored in a non-volatile fashion, the device can be used as a non-volatile memory device.
FIGS. 9(A)-(C) show an example of the basic structure of the MRAM. FIG. 9(A) shows a perspective view of the MRAM, and FIG. 9(B) schematically shows a circuit block diagram. FIG. 9(C) is a cross-section of an example of the structure of the MRAM. Referring to FIG. 9(A), in an MRAM, a word line WL and a bit line BL are disposed in an intersecting manner, with an MRAM cell disposed at each intersection. As shown in FIG. 9(B), the MRAM cell disposed at the intersection of a word line and a bit line comprises a MTJ device and a MOSFET directly connected to the MTJ device. Stored information can be read by reading the resistance value of the MTJ device that functions as a load resistance, using the MOSFET. The stored information can be rewritten by applying a magnetic field to the MTJ device, for example. As shown in FIG. 9(C), an MRAM memory cell comprises a MOSFET 100 including a source region 105 and a drain region 103 both formed inside a p-type Si substrate 101, and a gate electrode 111 formed on a channel region that is defined between the source and drain regions. The MRAM also comprises a MTJ device 117. The source region 105 is grounded, and the drain is connected to a bit line BL via the MTJ device. A word line WL is connected to the gate electrode 111 in a region that is not shown.
Thus, a single non-volatile MRAM memory cell can be formed by a single MOSFET 100 and a single MTJ device 117. The MRAMs are therefore suitable where high levels of integration are required.
- Non-Patent Document 1: D. Wang, et al.: Science 294 (2001) 1488.
特許請求の範囲(英語) [claim1]

1-2. (canceled)

[claim2]
3. A method of manufacturing a magnetoresistive random access memory (MRAM) comprising memory cells disposed at intersections of word lines and bit lines, each of the memory cells comprising a transistor connected with one of the word lines and a magnetic tunnel junction (MTJ) device connected with one of the bit lines, the method comprising:
forming a first CoFeB layer of the MTJ devices, the first CoFeB layer being amorphous;
forming a magnesium oxide (MgO) layer of the MTJ devices over the first CoFeB layer;
forming a second CoFeB layer of the MTJ devices, the second CoFeB layer being amorphous over the MgO layer; and
annealing the MTJ devices,
wherein the first and second CoFeB layers are crystallized by the annealing, and
wherein the MgO layer is poly-crystalline in which a (001) crystal plane is preferentially oriented.

[claim3]
4. The method of claim 3,
wherein after the annealing, the first and second CoFeB layers are entirely crystallized.

[claim4]
5. The method of claim 3,
wherein after the annealing, each of the first and second CoFeB layers is poly-crystalline in which a (001) crystal plane is preferentially oriented and each of the first and second CoFeB layers includes a BCC (body-centered cubic) structure.

[claim5]
6. The method of claim 3, wherein after the annealing,
the first and second CoFeB layers are entirely crystallized, and
each of the first and second CoFeB layers is poly-crystalline in which a (001) crystal plane is preferentially oriented and each of the first and second CoFeB layers includes a BCC (body-centered cubic) structure.

[claim6]
7. The method of claim 3,
wherein in the forming the MgO layer, the MgO layer is formed as a MgOx (0<x<1) layer.

[claim7]
8. The method of claim 3,
wherein in the forming the MgO layer, the MgO layer is formed directly on the first CoFeB layer.

[claim8]
9. The method of claim 3, wherein:
in the forming the MgO layer, the MgO layer is formed directly on the first CoFeB layer, and
in the forming the second CoFeB layer, the second CoFeB layer is formed directly on the MgO layer.

[claim9]
10. The method of claim 3,
wherein after the annealing, the MTJ devices are (001) oriented poly-crystal MTJ devices.

[claim10]
11. A method of manufacturing a magnetoresistive random access memory (MRAM) comprising memory cells, each of the memory cells comprising a transistor and a magnetic tunnel junction (MTJ) device, the method comprising:
forming a first ferromagnetic layer of the MTJ devices, the first ferromagnetic layer including a first CoFeB layer that is amorphous;
forming a barrier layer of the MTJ devices, the barrier layer including a magnesium oxide (MgO) layer to have a poly-crystalline state in which a (001) crystal plane is preferentially oriented over the first ferromagnetic layer,
forming a second ferromagnetic layer of the MTJ devices, the second ferromagnetic layer including a second CoFeB layer that is amorphous over the barrier layer; and
annealing the MTJ devices to crystallize the first and second CoFeB layers.

[claim11]
12. The method of claim 11,
wherein after the annealing, the first and second CoFeB layers are entirely crystallized.

[claim12]
13. The method of claim 11, wherein after the annealing,
the first and second CoFeB layers are entirely crystallized, and
each of the first and second CoFeB layers is poly-crystalline in which a (001) crystal plane is preferentially oriented and each of the first and second CoFeB layers includes a BCC (body-centered cubic) structure.

[claim13]
14. The method of claim 11,
wherein in the forming the barrier layer, the value of x in MgOx for the MgO layer is greater than 0 and less than 1.

[claim14]
15. The method of claim 11, wherein:
in the forming the barrier layer, the barrier layer is formed directly on the first ferromagnetic layer, and
in the forming the second ferromagnetic layer, the second ferromagnetic layer is formed directly on the barrier layer.

[claim15]
16. The method of claim 11,
wherein after the annealing, the MTJ devices are (001) oriented poly-crystal MTJ devices.

[claim16]
17. A method of manufacturing a magnetoresistive random access memory (MRAM) comprising:
forming transistors on a Si substrate;
forming word lines;
forming a first CoFeB layer of magnetic tunnel junction (MTJ) devices, the first CoFeB layer being amorphous;
forming a magnesium oxide (MgO) layer of the MTJ devices over the first CoFeB layer;
forming a second CoFeB layer of the MTJ devices, the second CoFeB layer being amorphous over the MgO layer;
forming bit lines which intersect with the word lines at intersections, regions of the intersections including one of the transistors and one of the MTJ devices; and
annealing the MTJ devices to form (001) oriented poly-crystal MTJ devices.

[claim17]
18. The method of claim 17,
wherein after the annealing, the first and second CoFeB layers are entirely crystallized.

[claim18]
19. The method of claim 17, wherein after the annealing,
the first and second CoFeB layers are entirely crystallized, and
each of the first and second CoFeB layers is poly-crystalline in which a (001) crystal plane is preferentially oriented and each of the first and second CoFeB layers includes a BCC (body-centered cubic) structure.

[claim19]
20. The method of claim 17,
wherein in the forming the MgO layer, the MgO layer is formed as a MgOx (0<x<1) layer.

[claim20]
21. The method of claim 17,
wherein in the forming the MgO layer, the MgO layer is poly-crystalline in which a (001) crystal plane is preferentially oriented.

[claim21]
22. The method of claim 17,
wherein the MgO layer is poly-crystalline in which a (001) crystal plane is preferentially oriented.
  • 発明者/出願人(英語)
  • YUASA SHINJI
  • NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
国際特許分類(IPC)
参考情報 (研究プロジェクト等) PRESTO Nanostructure and Material Property AREA
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