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Electronic circuit providing different hysteresis in two operation modes NEW

外国特許コード F200010268
整理番号 J1013-04EP2
掲載日 2020年11月9日
出願国 欧州特許庁(EPO)
出願番号 19216507
公報番号 3644505
出願日 平成28年3月24日(2016.3.24)
公報発行日 令和2年4月29日(2020.4.29)
国際出願番号 JP2016059453
国際公開番号 WO2016158691
国際出願日 平成28年3月24日(2016.3.24)
国際公開日 平成28年10月6日(2016.10.6)
優先権データ
  • 特願2015-075481 (2015.4.1) JP
  • 20160772572 (2016.3.24) EP
  • 2016JP59453 (2016.3.24) WO
発明の名称 (英語) Electronic circuit providing different hysteresis in two operation modes NEW
発明の概要(英語) Provided is an electronic circuit including: a bistable circuit connected between a positive power source and a negative power source that are supplied with power-supply voltages, the bistable circuit including a first inverter and a second inverter connected in a loop, the first inverter and the second inverter being inverter circuits configured to switch between a first mode and a second mode; a control circuit 20 configured to output a first signal and a second signal to the inverter circuits, the fist signal setting the inverter circuits in the first mode, the second signal setting the inverter circuits in the second mode; and a power-supply circuit 30 configured to supply a first voltage as the power-supply voltage while the inverter circuits are in the first mode, and supply a second voltage higher than the first voltage as the power-supply voltage while the inverter circuits are in the second mode, wherein the first mode is a mode that exhibits hysteresis in a transfer characteristic and the second mode is a mode that exhibits no hysteresis in a transfer characteristic, and/or the first mode is a mode of which the transfer characteristic is steeper than the transfer characteristic of the second mode.
従来技術、競合技術の概要(英語) BACKGROUND ART
A power gating (PG) technology has been proposed as a technology to reduce the power consumption of integrated circuits such as complementary metal oxide semiconductor (CMOS) integrated circuits and the like. One of the challenges in the power gating technology is retaining information at the time of power shut-down. To retain information at the time of power shut-down, using a non-volatile circuit such as a non-volatile memory for a memory circuit has been studied (Patent Document1). A low-voltage driving technique has been also studied to reduce the power consumption of the integrated circuit.
特許請求の範囲(英語) [claim1]
1. An electronic circuit characterized by comprising:
an inverter circuit (10) including:
one or more first P-channel FETs (11, 12) of which sources are coupled to a first power source supplied with a first power-supply voltage;
one or more first N-channel FETs (13, 14) of which sources are coupled to a second power source supplied with a second power-supply voltage lower than the first power-supply voltage, the one or more first P-channel FETs (11, 12) and/or the one or more first N-channel FETs (13, 14) are a plurality of first FETs connected in series;
an input node (Nin) to which gates of the one or more first P-channel FETs (11, 12) and gates of the one or more first N-channel FETs (13, 14) are commonly coupled;
an output node (Nout) to which a drain of an FET farthest from the first power source of the one or more first P-channel FETs (12) and a drain of an FET farthest from the second power source of the one or more first N-channel FETs (13) are commonly coupled; and
a second FET (15, 16) that is at least one of a second P-channel FET (15) and a second N-channel FET (16) that are of a conductive type identical to a conductive type of the plurality of first FETs, one of a source and a drain of the second FET (15, 16) being coupled to an intermediate node (Nm1, Nm2) located between the plurality of first FETs, a gate of the second FET being coupled to the output node (Nout), and another of the source and the drain of the second FET (15, 16) being coupled to a control node (NFP, NFN) ; and
a control circuit (20) configured to output a first signal and a second signal to a control node (NFP, NFN) of the second FET (15, 16), the first signal setting the inverter circuit (10) in a first mode, the second signal setting the inverter circuit (10) in a second mode, wherein
the control circuit (20) is configured to output, as the first signal, a low level to a control node (NFP) of the second P-channel FET (15)_and/or a high level to a control node (NFN) of the second N-channel FET (16), and output, as the second signal, a high level to the control node (NFP) of the second P-channel FET (15) and/or a low level to the control node (NFN) of the second N-channel FET (16), and
the first mode is a mode that exhibits hysteresis in a transfer characteristic curve, the second mode is a mode that exhibits no hysteresis in a transfer characteristic curve, and/or the first mode is a mode of which the transfer characteristic curve is steeper than the transfer characteristic curve of the second mode.

[claim2]
2. The electronic circuit according to claim 1, characterized in that
the one or more first P-channel FETs (11,12) are connected in series in a plurality and the one or more first N-channel FETs (13,14) are connected in series in a plurality;
the second FET (15, 16) includes the second P-channel FET (15) and the second N-channel FET (16); and
the control circuit (20) is configured to output, as the first signal, a low level to the control node (NFP) of the second P-channel FET (15) and a high level to the control node (NFN) of the second N-channel FET (16), and output, as the second signal, a high level to the control node of (NFP) the second P-channel FET (15) and a low level to the control node (NFN) of the second N-channel FET (16).

[claim3]
3. The electronic circuit according to claim 1 or 2, characterized by further comprising:
a power-supply circuit (30) configured to supply a first voltage as a power-supply voltage, which is a difference between the first power-supply voltage and the second power-supply voltage, while the inverter circuit (10) is in the first mode, and supply a second voltage higher than the first voltage as the power-supply voltage while the inverter circuit (10) is in the second mode.

[claim4]
4. The electronic circuit according to claim 3, characterized by further comprising
a logic circuit including the inverter circuit.
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • SUGAHARA SATOSHI
  • YAMAMOTO SHUICHIRO
国際特許分類(IPC)
指定国 Contracting States: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
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