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Electronic circuit with different hysteresis in two operation modes NEW

外国特許コード F200010269
整理番号 J1013-04EP3
掲載日 2020年11月9日
出願国 欧州特許庁(EPO)
出願番号 19216540
公報番号 3644506
出願日 平成28年3月24日(2016.3.24)
公報発行日 令和2年4月29日(2020.4.29)
国際出願番号 JP2016059453
国際公開番号 WO2016158691
国際出願日 平成28年3月24日(2016.3.24)
国際公開日 平成28年10月6日(2016.10.6)
優先権データ
  • 特願2015-075481 (2015.4.1) JP
  • 20160772572 (2016.3.24) EP
  • 2016JP59453 (2016.3.24) WO
発明の名称 (英語) Electronic circuit with different hysteresis in two operation modes NEW
発明の概要(英語) Provided is an electronic circuit including: a bistable circuit connected between a positive power source and a negative power source that are supplied with power-supply voltages, the bistable circuit including a first inverter and a second inverter connected in a loop, the first inverter and the second inverter being inverter circuits configured to switch between a first mode and a second mode; a control circuit 20 configured to output a first signal and a second signal to the inverter circuits, the fist signal setting the inverter circuits in the first mode, the second signal setting the inverter circuits in the second mode; and a power-supply circuit 30 configured to supply a first voltage as the power-supply voltage while the inverter circuits are in the first mode, and supply a second voltage higher than the first voltage as the power-supply voltage while the inverter circuits are in the second mode, wherein the first mode is a mode that exhibits hysteresis in a transfer characteristic and the second mode is a mode that exhibits no hysteresis in a transfer characteristic, and/or the first mode is a mode of which the transfer characteristic is steeper than the transfer characteristic of the second mode.
従来技術、競合技術の概要(英語) BACKGROUND ART
A power gating (PG) technology has been proposed as a technology to reduce the power consumption of integrated circuits such as complementary metal oxide semiconductor (CMOS) integrated circuits and the like. One of the challenges in the power gating technology is retaining information at the time of power shut-down. To retain information at the time of power shut-down, using a non-volatile circuit such as a non-volatile memory for a memory circuit has been studied (Patent Document1). A low-voltage driving technique has been also studied to reduce the power consumption of the integrated circuit.
特許請求の範囲(英語) [claim1]
1. An electronic circuit characterized by comprising:
a bistable circuit (40) connected between a first power source supplied with a first power-supply voltage and a second power source supplied with a second power-supply voltage lower than the first power-supply voltage, the bistable circuit (40) including: a first inverter (10a) and a second inverter (10b) that form a loop; and a switch (44) that turns on and off in synchronization with a clock signal (C, CB) and is located in the loop;
a clock supply circuit (46) configured to supply the clock signal (C, CB) to the switch (44); and
a power-supply circuit configured to supply a first voltage as [[the]] a power-supply voltage, which is a difference between the first power-supply voltage and the second power-supply voltage, while the clock supply circuit (46) is not supplying the clock signal (C,CB), and supply a second voltage higher than the first voltage as the power-supply voltage while the clock supply circuit (46) is supplying the clock signal (C, CB).
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • SUGAHARA SATOSHI
  • YAMAMOTO SHUICHIRO
国際特許分類(IPC)
指定国 Contracting States: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
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