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ELECTRONIC CIRCUIT AND BISTABLE CIRCUIT 新技術説明会

外国特許コード F210010308
整理番号 J1013-06WO
掲載日 2021年1月29日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2020JP012099
国際公開番号 WO 2020241000
国際出願日 令和2年3月18日(2020.3.18)
国際公開日 令和2年12月3日(2020.12.3)
優先権データ
  • 特願2019-101720 (2019.5.30) JP
  • 特願2019-186042 (2019.10.9) JP
発明の名称 (英語) ELECTRONIC CIRCUIT AND BISTABLE CIRCUIT 新技術説明会
発明の概要(英語) Provided is an electronic circuit equipped with: a cell array comprising a plurality of memory cells, each of the memory cells being equipped with a bistable circuit equipped with a first inverter circuit and a second inverter circuit that switch between a first mode in which a transfer characteristic does not substantially have hysteresis and a second mode in which the transfer characteristic has hysteresis, an output node and an input node of the first inverter circuit being connected to an input node and an output node of the second inverter circuit, respectively; and a control circuit that, after one or more first memory cells not required to hold data among the plurality of memory cells are powered off, puts the bistable circuit in the remaining one or more second memory cells among the plurality of memory cells into the second mode, and, while the second mode is being maintained, supplies, to the bistable circuit in one or more second memory cells, second power supply voltage which is lower than first power supply voltage to be supplied to the bistable circuit at the time of reading and/or writing of data and at which the bistable circuit in the second mode can hold the data.
従来技術、競合技術の概要(英語) BACKGROUND ART
It is known that a pseudo nonvolatile SRAM (VNR-SRAM) can be configured using an inverter configured only of CMOS (Complementary Metal Oxide Semiconductor) without using a nonvolatile element (, for example, Patent Document 1). In VNR-SRAM, a dual mode inverter capable of switching between a Schmitt trigger (ST) mode capable of ultra low voltage (ULV) retention and a boost inverter (BI) mode capable of achieving circuit performance equivalent to SRAM at normal voltage is used. This ULV retention can be used for power gating (PG).
A memory circuit using a memory cell (NV-SRAM) having a bistable circuit and a non-volatile element is known (, such as Patent Document 2). At NV-SRAM, the data of the bistable circuit is stored in the non-volatile element and the data of the non-volatile element is restored to the bistable circuit.
At NV-SRAM, a SRAM (Static Random Access Memory) operation of writing (and reading) data to a bistable circuit like a normal SRAM, a sleep operation of lowering a power supply voltage and holding data, A memory circuit is known that performs a store operation for storing data of a bistable circuit in a non-volatile element, a shutdown operation for shutting down a power supply of a memory cell, and a restore operation for writing data stored in the non-volatile memory element back to the bistable circuit (, for example, Patent Document 3). Using store, shutdown, and restore operations enables power gating (PG) by power interruption without losing the storage content of the cell.
A storage circuit is known that, when data stored in a bistable circuit matches data stored in a non-volatile element, performs control (that skips store a store free operation) (, such as Patent Document 4). It is known that a cell array is divided into a plurality of blocks, and the power of the block for which the store operation has been completed is turned off (, for example, Patent Document 5).
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • SUGAHARA, Satoshi
  • KITAGATA, Daiki
  • YAMAMOTO, Shuichiro
国際特許分類(IPC)
指定国 National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JO JP KE KG KH KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN WS ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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