Top > Search of International Patents > Computation device and computation system

Computation device and computation system UPDATE_EN

Foreign code F210010354
File No. 08672-US
Posted date Apr 7, 2021
Country United States of America
Application number 201816611971
Gazette No. 20200364031
Date of filing May 11, 2018
Gazette Date Nov 19, 2020
International application number JP2018018400
International publication number WO2018207926
Date of international filing May 11, 2018
Date of international publication Nov 15, 2018
Priority data
  • P2017-095803 (May 12, 2017) JP
  • 2018JP18400 (May 11, 2018) WO
Title Computation device and computation system UPDATE_EN
Abstract A computation device includes: a data multiplexer configured to output first high-order data as first output data and fifth output data, output first low-order data as third output data and seventh output data, output second high-order data as second output data, output second low-order data as fourth output data, output third high-order data, which is high-order data having a second bit number out of third input data, as sixth output data, and output third low-order data, which is low-order data having the second bit number out of the third input data, as eighth output data when a mode signal indicates a second computation mode; and first to fourth multipliers each of which multiplies two output data.
Outline of related art and contending technology BACKGROUND ART
Conventionally, single instruction multiple data (SIMD) computers capable of concurrently performing the same operation on a plurality of data have been known. For example, when a floating point operation unit is used for each operation unit constituting the SIMD computer, parallel floating point operations are realized by one core of a processor. In such an operation unit, the number of bits of data that can be supplied is constant, and thus, it is possible to switch between a first operation with double precision and a second operation with single precision by supplying four single-precision data instead of two double-precision data, for example (see, for example, Patent Literature 1).
Scope of claims [claim1]
1. A computation device comprising:
a multiplexer configured to receive first to third input data each having a first bit number and output first to eighth output data each having a second bit number that is half the first bit number in response to a mode signal indicating a computation mode;
a first multiplier configured to multiply the first output data and the second output data;
a second multiplier configured to multiply the third output data and the fourth output data;
a third multiplier configured to multiply the fifth output data and the sixth output data; and
a fourth multiplier configured to multiply the seventh output data and the eighth output data,
wherein the multiplexer outputs first high-order data, which is high-order data having the second bit number out of the first input data, as the first output data and the fifth output data, outputs first low-order data, which is low-order data having the second bit number out of the first input data, as the third output data and the seventh output data, outputs second high-order data, which is high-order data having the second bit number out of the second input data, as the second output data and the fourth output data, and outputs second low-order data, which is low-order data having the second bit number out of the second input data, as the sixth output data and the eighth output data when the mode signal indicates a first computation mode using data having the first bit number, and
the multiplexer outputs the first high-order data as the first output data and the fifth output data, outputs the first low-order data as the third output data and the seventh output data, outputs the second high-order data as the second output data, outputs the second low-order data as the fourth output data, outputs third high-order data, which is high-order data having the second bit number out of the third input data, as the sixth output data, and outputs third low-order data, which is low-order data having the second bit number out of the third input data, as the eighth output data when the mode signal indicates a second computation mode using data having the second bit number.

[claim2]
2. The computation device according to claim 1, further comprising:
a first adder configured to ad a first multiplication result that is a multiplication result of the first multiplier and a second multiplication result that is a multiplication result of the second multiplier;
a second adder configured to ad a third multiplication result that is a multiplication result of the third multiplier and a fourth multiplication result that is a multiplication result of the fourth multiplier; and
a partial adder configured to ad the first multiplication result, the second multiplication result, the third multiplication result, and the fourth multiplication result.

[claim3]
3. The computation device according to claim 2,
wherein the first multiplier outputs a first intermediate result and a second intermediate result, which are results obtained during the multiplication by the first multiplier, as the first multiplication result,
the second multiplier outputs a third intermediate result and a fourth intermediate result, which are results obtained during the multiplication by the second multiplier, as the second multiplication result,
the third multiplier outputs a fifth intermediate result and a sixth intermediate result, which are results obtained during the multiplication by the third multiplier, as the third multiplication result, and
the fourth multiplier outputs a seventh intermediate result and an eighth intermediate result, which are results obtained during the multiplication by the fourth multiplier, as the fourth multiplication result.

[claim4]
4. The computation device according to claim 2, further comprising:
a plurality of computation units each including the multiplexer, the first multiplier, the second multiplier, the third multiplier, the fourth multiplier, and the partial adder;
a third adder configured to ad addition results of the partial adders of the plurality of computation units; and
a selector configured to output any of a first addition result that is an addition result of the first adder and a second addition result that is an addition result of the second adder, and a third addition result that is an addition result of the third adder, in response to the mode signal,
wherein the first adder ads the first multiplication results and the second multiplication results of the plurality of computation units,
the second adder ads the third multiplication results and the fourth multiplication results of the plurality of computation units, and
the selector outputs the third addition result when the mode signal indicates the first computation mode and outputs the first addition result and the second addition result when the mode signal indicates the second computation mode.

[claim5]
5. The computation device according to claim 4, further comprising
a shift amount arithmetic circuit configured to compute a first shift amount of the first multiplication result, a second shift amount of the second multiplication result, a third shift amount of the third multiplication result, and a fourth shift amount of the fourth multiplication result,
wherein each of the plurality of computation units further includes: a first alignment unit configured to perform a shift process on the first multiplication result based on the first shift amount; a second alignment unit configured to perform a shift process on the second multiplication result based on the second shift amount; a third alignment unit configured to perform a shift process on the third multiplication result based on the third shift amount; and a fourth alignment unit configured to perform a shift process on the fourth multiplication result based on the fourth shift amount.

[claim6]
6. The computation device according to claim 5, wherein the shift amount arithmetic circuit includes: a maximum value arithmetic circuit configured to compute a maximum exponent, which is a maximum exponent part among exponent parts of a plurality of target data to be added; and a subtraction circuit configured to compute a difference between each of the plurality of target data and the maximum exponent as a shift amount.

[claim7]
7. The computation device according to claim 6, wherein the maximum value arithmetic circuit computes the maximum exponent by performing comparison in order from a most significant bit to a least significant bit of the plurality of target data.

[claim8]
8. The computation device according to claim 1,
wherein the first computation mode is a double-precision computation mode, and
the second computation mode is a single-precision computation mode.

[claim9]
9. The computation device according to claim 1,
wherein the first computation mode is a single-precision computation mode, and
the second computation mode is a half-precision computation mode.

[claim10]
10. A computation system comprising:
an arithmetic unit including a plurality of computation devices, the computation device according to claim 1; and
a plurality of processors sharing the arithmetic unit.

[claim11]
11. The computation system according to claim 10, wherein the plurality of processors operate as a single processor when performing a matrix operation, and operate as individual processors when performing an operation other than the matrix operation.

[claim12]
12. The computation system according to claim 10, wherein the plurality of processors perform a SIMD operation that operates with one instruction.

[claim13]
13. The computation system according to claim 10, further comprising
a memory space accessible by a memory address including a processor ID capable of uniquely identifying each of the plurality of processors,
wherein each of the plurality of processors is capable of accessing a memory area indicated by the memory address including the processor ID of the processor.

[claim14]
14. The computation system according to claim 13,
wherein the plurality of processors are ring-coupled, and
each of the plurality of processors sequentially transfers data having been received from the arithmetic unit to the other processors via the ring coupling.
  • Inventor, and Inventor/Applicant
  • MAKINO JUNICHIRO
  • MURANUSHI TAKAYUKI
  • NAMURA TAKOSHI
  • TSUBOUCHI MIYUKI
  • PREFERRED NETWORKS, INC.
  • RIKEN
IPC(International Patent Classification)

PAGE TOP

close
close
close
close
close
close