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Arithmetic operation device and arithmetic operation system UPDATE_EN meetings

Foreign code F210010355
File No. 08792-US
Posted date Apr 7, 2021
Country United States of America
Application number 202017037767
Gazette No. 20210011686
Date of filing Sep 30, 2020
Gazette Date Jan 14, 2021
Priority data
  • P2018-069568 (Mar 30, 2018) JP
  • 2019JP14330 (Mar 29, 2019) WO
Title Arithmetic operation device and arithmetic operation system UPDATE_EN meetings
Abstract Provided is an arithmetic operation device including a multiplying section in which multiplying units are divided and assigned to each of one or more groups such that each group includes one or more of the multiplying units according to a calculation precision mode, and each multiplying unit multiplies together an individual multiplier, which is a digit range of at least a portion of a multiplier for the group, and an individual multiplicand, which is a digit range of at least a portion of a multiplicand for the group, and an adding section in which adding units are divided and assigned to each of one or more groups such that each group includes one or more of the adding units according to the calculation precision mode, and the adding units add together each multiplication result obtained by each multiplying unit and output a product of the multiplier and the multiplicand.
Outline of related art and contending technology BACKGROUND
1. Technical Field
The present invention relates to an arithmetic operation device and an arithmetic operation system, particularly to an arithmetic operation device and an arithmetic operation system for performing multiplication with variable precision.
2. Related Art
A conventional apparatus is known that performs double-precision multiplication. For example, an arithmetic operation device disclosed in Patent Document 1 includes two multiplying units 12 and 13, an ALU 37, and accumulators 24 and 25. An input section of the ALU 37 is provided with multiplication results of the multiplying units 12 and 13 and the outputs of the accumulators 24 and 25.
Scope of claims [claim1]
1. An arithmetic operation device for performing multiplication with variable precision, comprising:
a multiplying section that includes a plurality of multiplying units, which are divided and assigned to each of one or more groups such that each group includes one or more of the multiplying units according to a calculation precision mode, wherein each multiplying unit in each group multiplies together an individual multiplier, which is a digit range of at least a portion of a multiplier for the group, and an individual multiplicand, which is a digit range of at least a portion of a multiplicand for the group, according to the calculation precision mode;
an adding section that includes a plurality of adding units, which are divided and assigned to each of the one or more groups such that each group includes one or more of the adding units according to the calculation precision mode, wherein the one or more adding units assigned to each group add together each multiplication result obtained by each multiplying unit assigned to the group and output a product of the multiplier and the multiplicand; and
a first connection switching unit for, for each of the one or more groups, inputting each multiplication result obtained by each multiplying unit to a digit position to which the multiplication result is to be added in the one or more adding units, according to the calculation precision mode.

[claim2]
2. The arithmetic operation device according to claim 1, wherein
each of the plurality of multiplying units multiplies together the individual multiplier and the individual multiplicand, and outputs the multiplication result that includes sum data of each digit and carry data of each digit.

[claim3]
3. The arithmetic operation device according to claim 1, wherein
each of the plurality of multiplying units multiplies together the individual multiplier and the individual multiplicand, which each have a 1-unit bit length, and outputs the multiplication result having a 2-unit bit length, and
each of the plurality of adding units adds together a plurality of pieces of input data, which each have a 2-unit bit length, and outputs a sum having a 2-unit bit length and, according to the calculation precision mode, a carry to a high-order digit.

[claim4]
4. The arithmetic operation device according to claim 1, wherein
in at least one calculation precision mode for multiplying together the multiplier and the multiplicand that each have a unit bit length of 2 or more, for each of the one or more groups:
in each cycle, the one or more multiplying units input the individual multipliers having digit ranges to be processed by each of the plurality of multiplying units in the multiplier and the individual multiplicands selected 1-unit-bit-length at a time in order from the high-order digit side in each cycle in the multiplicand, and output each partial product of the individual multipliers and the individual multiplicands in each cycle, as the multiplication result,
in each cycle, the first connection switching unit shifts each partial product output by the one or more multiplying units and inputs the shifted partial products to the one or more adding units to be added to an intermediate result such that the partial product of the individual multiplier and the individual multiplicand of the digit range on the lowest-order side in the multiplier corresponds to the lowest-order digit range in the one or more adding units, and
the arithmetic operation device further comprises a second connection switching unit for, for each of the one or more groups, in each cycle, shifting the intermediate result by 1 unit bit length toward a high-order side and inputting the shifted intermediate result to the one or more adding units.

[claim5]
5. The arithmetic operation device according to claim 4, wherein
in at least one calculation precision mode for unit bit lengths of 2 or more, the plurality of multiplying units and the plurality of adding units are assigned to two or more groups, and
the arithmetic operation device, for each of the two or more groups, calculates a product of the multiplier and the multiplicand using a plurality of cycles.

[claim6]
6. The arithmetic operation device according to claim 4, wherein
in a calculation precision mode for multiplying together the multiplier and the multiplicand that each have a 1-unit bit length:
the plurality of multiplying units are assigned to the plurality of groups, each of which includes one multiplying unit, and
the multiplying unit assigned to each group multiplies together the multiplier and the multiplicand that each have a 1-unit bit length assigned to the group.

[claim7]
7. The arithmetic operation device according to claim 4, wherein
the adding section includes a plurality of intermediate registers that are respectively provided corresponding to each of the plurality of adding units and each hold a digit range corresponding to the respective adding unit in the intermediate result.

[claim8]
8. The arithmetic operation device according to claim 7, wherein
each of the plurality of adding units includes a first adding element for outputting an addition result that includes sum data of each digit and carry data of each digit,
each of the plurality of intermediate registers holds the sum data and the carry data of a digit range output by the corresponding first adding element in the intermediate result, and
the adding section further includes a plurality of second adding elements, which are respectively provided corresponding to each of the plurality of adding units and are divided and assigned to each of the one or more groups such that each group includes one or more second adding elements according to the calculation precision mode, for adding together the sum data and the carry data output by the one or more first adding elements in each group and outputting the addition result as a product of the multiplier and the multiplicand.

[claim9]
9. An arithmetic operation device for performing multiplication with variable precision, comprising;
a multiplying section that includes a plurality of multiplying units that are each for multiplying together two numbers that each have a 1-unit bit length and outputting a multiplication result that includes sum data of each digit and carry data of each digit;
an adding section that includes a plurality of adding units that are each for adding together at least two pieces of input data including the multiplication result obtained by at least one multiplying unit among the plurality of multiplying units; and
a mode selecting section for selecting, according to a calculation precision mode, a number of divisions for dividing the plurality of multiplying units and the plurality of adding units into each group, each group including one or more multiplying units and one or more adding units and multiplying together a different multiplier and multiplicand, and the number of cycles used to multiply together the multiplier and the multiplicand using the one or more multiplying units and the one or more adding units in the group.

[claim10]
10. The arithmetic operation device according to claim 9, wherein
the mode selecting section, in a calculation precision mode for multiplying together the multiplier and the multiplicand that each have an n-bit unit length (n is a natural number), divides the plurality of multiplying units and the plurality of adding units into at least one of the groups that include n multiplying units and n adding units respectively,
the n multiplying units in each of the at least one group multiply together each of n individual multipliers, which each have a digit range of 1 unit bit length included in the multiplier of each group, and each of n individual multiplicands, which each have a digit range of 1 unit bit length included in the multiplicand, by n sets per cycle over n cycles, and
the n adding units in each of the at least one group are combined to, over n cycles, continuously add each multiplication result from the n multiplying units of the same group in each cycle to a digit position corresponding to each multiplication result in an intermediate result of the multiplier and the multiplicand.

[claim11]
11. An arithmetic operation system comprising:
an arithmetic unit that includes a plurality of arithmetic operation devices, each arithmetic operation device being the arithmetic operation device according to claim 1; and
a plurality of processors that share the arithmetic unit.
  • Inventor, and Inventor/Applicant
  • MAKINO JUNICHIRO
  • NITADORI KEIGO
  • TSUBOUCHI MIYUKI
  • RIKEN
IPC(International Patent Classification)

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