Arithmetic operation device and arithmetic operation system
外国特許コード  F210010407 

整理番号  08792CN 
掲載日  2021年5月7日 
出願国  中華人民共和国 
出願番号  201980024094 
公報番号  111971649 
出願日  平成31年3月29日(2019.3.29) 
公報発行日  令和2年11月20日(2020.11.20) 
国際出願番号  JP2019014330 
国際公開番号  WO2019189878 
国際出願日  平成31年3月29日(2019.3.29) 
国際公開日  令和元年10月3日(2019.10.3) 
優先権データ 

発明の名称 （英語）  Arithmetic operation device and arithmetic operation system 
発明の概要（英語）  Provided is an arithmetic operation device provided with: a multiplication section in which a plurality of multipliers are divided in units of one or more multipliers in accordance with an arithmeticoperation accuracy mode and allocated to one or more groups, and in each of the groups, each multiplier multiplies an individual multiplier factor within at least a partial digit range of a multiplierfactor for the group by an individual multiplicand within at least a partial digit range of a multiplicand for the group in accordance with the arithmetic operation accuracy mode; and an addition section in which a plurality of adders are divided in units of one or more adders in accordance with the arithmetic operation accuracy mode and allocated to one or more groups, and the one or more addersallocated to each of the groups add together the multiplication results of the respective multipliers allocated to the group, and output a product of the multiplier factors and the multiplicands. 
特許請求の範囲（英語） 
[claim1] 1. An arithmetic device for performing multiplication with variable accuracy, comprising: a multiplier unit having a plurality of multipliers divided for each of the multipliers according to an operation accuracy mode and allocated to each of one or more groups, each multiplier performing a multiplication operation on an individual multiplier, which is a bit range of at least a part of a multiplier corresponding to the group, and an individual multiplicand, which is a bit range of at least a part of a multiplicand corresponding to the group, according to the operation accuracy mode in each group; an adder unit having a plurality of adders which are divided for each of one or two or more adders according to an operation accuracy pattern and are assigned to each of the one or more groups, wherein the one or two or more adders assigned to each group add respective multiplication results obtained by the respective multipliers assigned to the group, and output a product of the multiplier and the multiplicand; and and a first connection switch for inputting each multiplication result obtained by each multiplier to a bit position to which the multiplication result is to be added in the one or more adders for each of the one or more groups according to an operation accuracy pattern. [claim2] 2. The arithmetic device according to claim 1, each of the plurality of multipliers multiplies the individual multiplier and the individual multiplicand, and outputs the multiplication result including sum data of each digit and carryin data from each digit. [claim3] 3. The arithmetic device according to claim 1 or 2, each of the multipliers multiplies the individual multiplier and the individual multiplicand by 1 unit bit length and outputs the multiplication result by 2 unit bit lengths, each of the adders adds a plurality of input data of 2 unit bit lengths and outputs a sum of the 2 unit bit lengths and a carry to a higher digit depending on the operation accuracy pattern. [claim4] 4. The arithmetic device according to any one of claims 1 to 3, in at least one operation precision mode for performing multiplication operation on the multiplier and the multiplicand with the length of more than 2 unit bits, with respect to each of the one or more groups, the one or more multipliers are input in each cycle with the individual multipliers of the range of digits of the multipliers for which the respective multipliers are responsible and the individual multiplicands of the multiplicands selected in order from the high digits in each cycle with a length of 1 unit bit, partial products of the individual multipliers and the individual multiplicands are output in each cycle as the multiplication operation result, the first connection switch shifts each partial product output from the one or more multipliers so that the partial product of the individual multiplier and the individual multiplicand in the bit range on the lowest order side of the multipliers corresponds to the lowest order bit range of the one or more adders, inputs the shifted partial product to the one or more adders, and adds the shifted partial product to an intermediate result in each cycle, the arithmetic device further includes a second connection switch that shifts the intermediate result by 1 unit bit length to the highorder side for each of the one or more groups and inputs the result to the one or more adders. [claim5] 5. The arithmetic device according to claim 4, in at least one operation precision mode of 2 unit bit lengths or more, the plurality of multipliers and the plurality of adders are allocated to two or more groups, the arithmetic device calculates a product of the multiplier and the multiplicand by using a plurality of cycles for each of the two or more groups. [claim6] 6. The arithmetic device according to claim 4 or 5, in an operation precision mode in which multiplication operations are performed on the multiplier and the multiplicand of 1 unit bit length, the plurality of multipliers are assigned to the plurality of groups each including one multiplier, the multiplier assigned to each group multiplies the multiplier and the multiplicand of 1 unit bit length assigned to the group. [claim7] 7. The arithmetic device according to any one of claims 4 to 6, the adder unit includes a plurality of intermediate registers provided corresponding to the adders, respectively, and each of the intermediate registers holds a bit range corresponding to each of the adders in the intermediate result. [claim8] 8. The arithmetic device according to claim 7, each of the plurality of adders including a first addition element that outputs an addition result including sum data of each digit and carry data from each digit, the plurality of intermediate registers each holding sum data and carry data of a range of digits output by a corresponding first adding element in the intermediate result, the adder unit further includes a plurality of second adding elements provided in correspondence with the respective adders, the plurality of second adding elements being divided for each or every two or more second adding elements according to an operation accuracy pattern and assigned to the respective groups, and the plurality of second adding elements adding the sum data and the carry data output from the one or more first adding elements in the respective groups and outputting the sum data and the carry data as a product of the multiplier and the multiplicand. [claim9] 9. An arithmetic device for performing multiplication with variable accuracy, comprising: a multiplier unit having a plurality of multipliers each of which multiplies two numbers of 1 unit bit length and outputs a multiplication result including sum data of each number of bits and carryin data from each number of bits; an adder unit having a plurality of adders each of which adds at least two input data including the multiplication result obtained by at least one of the plurality of multipliers; and and a mode selection unit that selects, in accordance with an operation accuracy mode, a division number that divides the plurality of multipliers and the plurality of adders into groups, the group including one or more multipliers and one or more adders, and that multiplies mutually different multipliers and multiplicands, and a cycle number that is used when the one or more multipliers and the one or more adders are used in the group to multiply the multipliers and the multiplicands. [claim10] 10. The arithmetic device according to claim 9, the mode selector divides the multipliers and the adders into at least one of the groups each including n multipliers and n adders in an operation accuracy mode in which the multipliers and the multiplicands of n unit bit lengths are multiplied, where n is a natural number, the n multipliers in each of at least one of the groups perform multiplication of each of n individual multipliers of each of the groups by each of n individual multiplicands of the n individual multiplicands in one cycle, each of the n individual multipliers being a range of 1 unit bit length of digits contained in the multiplier, and each of the n individual multiplicands being a range of 1 unit bit length of digits contained in the multiplicand, in a period of n cycles, the n adders in each of at least one of the groups are grouped together, and each multiplication result from the n multipliers of the same group in each cycle is added to a bit position corresponding to each multiplication result in an intermediate result of a product of the multiplier and the multiplicand during n cycles. [claim11] 11. An arithmetic system includes: an arithmetic unit provided with a plurality of arithmetic devices according to any one of claims 1 to 10; and a plurality of processors sharing the arithmetic unit. 




国際特許分類(IPC) 

日本語項目の表示
発明の概要  複数の乗算器が演算精度モードに応じて１または２以上の乗算器毎に分割されて１または複数のグループのそれぞれに割り当てられ、各グループにおいて各乗算器が演算精度モードに応じて当該グループに対する乗数の少なくとも一部の桁範囲である個別乗数および当該グループに対する被乗数の少なくとも一部の桁範囲である個別被乗数を乗算する乗算部と、複数の加算器が演算精度モードに応じて１または２以上の加算器毎に分割されて１または複数のグループのそれぞれに割り当てられ、各グループに割り当てられた１または２以上の加算器が当該グループに割り当てられた各乗算器による各乗算結果を加算して乗数および被乗数の積を出力する加算部とを備える演算装置を提供する。 





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