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Tunneling field effect transistor

外国特許コード F210010521
整理番号 AF41-02WO
掲載日 2021年7月30日
出願国 中華人民共和国
出願番号 201880076199
公報番号 112292762
出願日 平成30年11月28日(2018.11.28)
公報発行日 令和3年1月29日(2021.1.29)
国際出願番号 JP2018043787
国際公開番号 WO2019107411
国際出願日 平成30年11月28日(2018.11.28)
国際公開日 令和元年6月6日(2019.6.6)
優先権データ
  • 201762591798 (2017.11.29) US
  • 2018JP43787 (2018.11.28) WO
発明の名称 (英語) Tunneling field effect transistor
発明の概要(英語) A tunneling field effect transistor according to an embodiment of the present invention includes: a first semiconductor layer of a first conductive type; a second semiconductor layer of a second conductive type, the second conductive layer forming, in a first region, a hetero-junction with the first semiconductor layer; a gate insulating layer covering the second semiconductor layer in the first region; a gate electrode layer that covers the gate insulating layer; a first electrode layer electrically connected to the first semiconductor layer; a second electrode layer electrically connected tothe second semiconductor layer; and a first insulating layer which in a second region is sandwiched between the first semiconductor layer and the second semiconductor layer, the second region being adjacent to the second electrode layer side with respect to the first region.
特許請求の範囲(英語) [claim1]
1. A tunneling field effect transistor, comprising:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type, which realizes a heterojunction with the first semiconductor layer in a first region;
a gate insulating layer covering the second semiconductor layer in the first region;
a gate electrode layer covering the gate insulating layer;
a first electrode layer electrically connected to the first semiconductor layer;
a second electrode layer electrically connected to the second semiconductor layer;
a first insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer in a second region adjacent to the first region on the second electrode layer side.

[claim2]
2. The tunneling field effect transistor of claim 1,
the first semiconductor layer and the second semiconductor layer are materials having an energy band structure forming a type II energy band structure by the heterojunction.

[claim3]
3. The tunneling field effect transistor of claim 2,
the second semiconductor layer is a material whose energy at the lower end of the conduction band is within the band gap of the first semiconductor layer.

[claim4]
4. The tunneling field effect transistor of claim 3,
the second semiconductor layer is formed of a material having a band gap larger than that of the first semiconductor layer.

[claim5]
5. The tunneling field effect transistor of claim 1,
the first semiconductor layer is a p-type semiconductor,
the second semiconductor layer is an n-type semiconductor.

[claim6]
6. The tunneling field effect transistor of claim 5,
the first semiconductor layer is a group IV semiconductor,
the second semiconductor layer is a II-VI semiconductor.

[claim7]
7. The tunneling field effect transistor of claim 5,
the first semiconductor layer is a group IV semiconductor,
the second semiconductor layer contains a metal oxide.

[claim8]
8. The tunneling field effect transistor of claim 7,
the first semiconductor layer contains Si.

[claim9]
9. The tunneling field effect transistor of claim 7,
the first semiconductor layer contains Si and Ge.

[claim10]
10. The tunneling field effect transistor of claim 1,
the first semiconductor layer is an n-type semiconductor,
the second semiconductor layer is a p-type semiconductor.

[claim11]
11. The tunneling field effect transistor of claim 1,
the second semiconductor layer has a dielectric constant lower than that of the first semiconductor layer.

[claim12]
12. The tunneling field effect transistor of claim 1,
the gate insulating layer and the gate electrode layer are arranged so as to extend from the first region to the second region.

[claim13]
13. The tunneling field effect transistor of claim 1,
the second region is adjacent to the first region on the first electrode layer side.

[claim14]
14. The tunneling field effect transistor of claim 1,
the second region surrounds the first region.

[claim15]
15. The tunneling field effect transistor of claim 1,
in a portion where the heterojunction is realized, a bonding insulating layer whose component contains the first semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer.

[claim16]
16. The tunneling field effect transistor of claim 15,
the first semiconductor layer is a p-type semiconductor,
the second semiconductor layer is an n-type semiconductor,
the bonding insulating layer contains an oxide of the first semiconductor layer.

[claim17]
17. The tunneling field effect transistor of claim 15,
the first semiconductor layer is an n-type semiconductor,
the second semiconductor layer is a p-type semiconductor,
the bonding insulating layer contains an oxide of the second semiconductor layer.

[claim18]
18. A tunneling field effect transistor, comprising:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type which realizes a heterojunction with respect to the first semiconductor layer in the first region;
a gate insulating layer covering the second semiconductor layer in the first region;
a gate electrode layer covering the gate insulating layer;
a first electrode layer electrically connected to the first semiconductor layer; and
a second electrode layer electrically connected to the second semiconductor layer,
in the case where the surface of the heterojunction is viewed perpendicularly, a region where the first semiconductor layer and the second semiconductor layer overlap is wider than the first region.

[claim19]
19. An electronic device, comprising:
a plurality of tunneling field effect transistors according to any one of claims 1 to 18; and
and a conductor for supplying a signal to the tunneling field effect transistor.

[claim20]
20. The electronic device of claim 19,
the plurality of tunneling field effect transistors includes at least an N-channel tunneling field effect transistor and a P-channel tunneling field effect transistor,
the N-channel tunneling field effect transistor is connected with the P-channel tunneling field effect transistor through the conductor.
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • KATO KIMIHIKO
  • TAKAGI SHINICHI
  • TAKENAKA MITSURU
  • TABATA HITOSHI
  • MATSUI HIROAKI
国際特許分類(IPC)
参考情報 (研究プロジェクト等) CREST Innovative nano-electronics through interdisciplinary collaboration among material, device and system layers AREA
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