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Electronic circuit and bistable circuit

外国特許コード F210010525
整理番号 J1013-06TW
掲載日 2021年7月30日
出願国 台湾
出願番号 109110825
公報番号 202044252
出願日 令和2年3月30日(2020.3.30)
公報発行日 令和2年12月1日(2020.12.1)
優先権データ
  • 特願2019-101720 (2019.5.30) JP
  • 特願2019-186042 (2019.10.9) JP
発明の名称 (英語) Electronic circuit and bistable circuit
発明の概要(英語) Provided is an electronic circuit equipped with: a cell array comprising a plurality of memory cells, each of the memory cells being equipped with a bistable circuit equipped with a first inverter circuit and a second inverter circuit that switch between a first mode in which a transfer characteristic does not substantially have hysteresis and a second mode in which the transfer characteristic has hysteresis, an output node and an input node of the first inverter circuit being connected to an input node and an output node of the second inverter circuit, respectively; and a control circuit that, after one or more first memory cells not required to hold data among the plurality of memory cells are powered off, puts the bistable circuit in the remaining one or more second memory cells among the plurality of memory cells into the second mode, and, while the second mode is being maintained, supplies, to the bistable circuit in one or more second memory cells, second power supply voltage which is lower than first power supply voltage to be supplied to the bistable circuit at the time of reading and/or writing of data and at which the bistable circuit in the second mode can hold the data.
従来技術、競合技術の概要(英語) Background of the Invention]
The present invention relates to electronic circuits and bistable circuits, to, for example, bistable circuits and to electronic circuits provided with a plurality of memory cells ( memory cell ) having the bistable circuits.
[Prior Art]
It is now known that it is possible not to use non-volatile elements, but rather to use inverters composed of only CMOS ( Complementary Metal Oxide Semiconductor , complementary metal oxide semiconductors), to construct similar non-volatile SRAM ( VNR-SRAM ) (e. g. patent document 1 ). In VNR-SRAM, is a dual mode inverter using switchable modes ( dual-mode inverter ) : ultra low voltage ( ULV ) Smitt flip-flop holding ( retention ) ( Schmitt trigger ) ( ST ) mode, and a high voltage inverter operating in a low voltage mode. And a boost inverter ( boosted inverter ) ( BI ) mode in which the same circuit performance as SRAM can be achieved at a typical voltage. This ULV may be saved for power gating ( power gating ) ( PG ).
Memory circuits (using memory cells ( NV-SRAM ) with bi-stable circuits and non-volatile elements are known, for example, from Patent Document 2 ). In NV-SRAM, the data for the bistable circuit is stored in non-volatile element, and the data for the non-volatile element is stored back ( restore /to the bistable circuit).
In NV-SRAM, there are currently known memory circuits (e. g. patent document 3 ) : SRAM ( Static Random Access Memory ) actions to write data ( write ) to bistable circuits and read ( read ) as generally SRAM. The method includes the steps of reducing the power supply voltage to maintain the dormant action of the data, storing the data of the bistable circuit in the storage action of the non-volatile element, disabling the power supply of the memory cell ( shutdown ), and writing the stored data of the non-volatile memory element back to the storage action of the bistable circuit. By using storage, shutdown, and rebound actions, it is possible without losing memory content of the unit, to make the power gate ( PG ) available for power shut-off.
It is currently known that a memory circuit (such as Patent Document 4 ) , is a control for skipping ( skip ) storage (free of storage action) in the event that the data stored by the bistable circuit is consistent with the data stored by the non-volatile components. There are currently known ways to divide the cell array into a plurality of blocks, and to disconnect power from blocks whose storage action has ended (e. g. patent document 5 ). Prior art Document Patent Document.
Patent Document 1 : International Publication No. 2016/158691 Patent Document 2 : International Publication No. 2009/028298 Patent Document 3 : International Publication No. 2013/172066 Patent Document 4 : International Publication No. 2013/172065 Patent Document 5 : International Publication No. 2016/024527
特許請求の範囲(英語) [claim1]
1. An electronic circuit, having an array of: cells, having a plurality of memory cells having bistable circuits, each memory cell having 1 inverter circuits for switching 1 mode and 2 mode and 2 inverter circuits, The aforementioned 1 th mode is a mode with substantially no hysteresis in transfer characteristics, the aforementioned 2 th mode is a mode with hysteresis in transfer characteristics, the output node and the input node of the aforementioned 1 th inverter circuit are connected to the input node and the output node of the aforementioned 2 th inverter circuit;, respectively. And control circuit, after power is turned off for 1 or 1 th of the plurality of memory cells that may also not maintain data, the remaining 1 or 2 th of the plurality of memory cells is set to 2 th mode, In the state where the aforementioned 2 th mode is maintained, the 1 th supply voltage to the bistable circuit will be lower than when reading and/or writing data and the bistable circuit of the aforementioned 2 th mode can maintain the 2 th supply voltage, of the data to the bistable circuit within the aforementioned 1 or more 2 th memory cells.

[claim2]
2. An electronic circuit as claimed in claim 1, wherein said array of cells is a plurality of blocks divided into blocks containing at least 2 memory cells in each block, said control circuit is a 1 th block or 1 th block or 1 th block or 1 th block or 1 th block or 1 th block, The bistable circuit in the remaining 1 or 2 th block of the aforementioned plurality of blocks is set to the aforementioned 2 th mode, The aforementioned 2 th power supply voltage is supplied to the bistable circuit in the aforementioned 1 or 2 th block while maintaining the aforementioned 2 th mode,.

[claim3]
3. The electronic circuit of claim 2, wherein said control circuit is a supply voltage that supplies a 3 th supply voltage to said 1 or 2 th block, before said bistable circuit in said 1 or 2 th block is set to said 2 th mode, and said 3 th supply voltage is a supply voltage that is lower than said 1 th supply voltage and higher than said 2 th supply voltage, and said bistable circuit of said 1 th mode can maintain data.

[claim4]
4. The electronic circuit, of claim 3 wherein said control circuit is a state in which said 3 th supply voltage has been supplied to said bistable circuit in said 1 or 2 th block, and said bistable circuit in said 1 or 2 th block is set to said 2 th mode.

[claim5]
5. The electronic circuit of claim 3, wherein said 1 or more 2 th block is a plurality of 2 th block, said control circuit is in a state that said 3 th supply voltage has been supplied to a bi-stable circuit of 1 or more of said plurality of 2 th block, Setting the bistable circuits in the aforementioned 1 or 3 th block to the aforementioned 2 th mode, Supply the aforementioned 2 th power supply voltage, in a state where the bistable circuits in the aforementioned 1 or 3 th block have been set to the aforementioned 2 th mode. Thereafter, In the state where the aforementioned 3 th power supply voltage has been supplied to the bistable circuits of 1 or 4 th blocks different from the aforementioned 1 or 4 th blocks, the bistable circuits in the aforementioned 1 or 4 th blocks are set to the aforementioned 2 th mode, and the aforementioned 2 th power supply voltage has been supplied in the state where the bistable circuits in the aforementioned 1 or 4 th blocks have been set to the aforementioned 2 th mode.

[claim6]
6. The electronic circuit of claim 3, wherein said 1 or 2 th block is a plurality of 2 th blocks, said control circuit is in a state that said 3 th supply voltage has been supplied to said bistable circuit in said plurality of 2 th blocks, after said bistable circuit in said plurality of 2 th blocks has been set to said 2 th mode, after said bistable circuit in said plurality of 2 th blocks has been set to said 2 th mode.

[claim7]
7. An electronic circuit as claimed in claim 2, provided with memory circuits, said memory circuits being arranged outside said array of cells, and memory display information which also does not hold blocks of said data received from external circuits, said control circuit is based on said information, to extract said 1 th or 1 th blocks which also do not hold said data.

[claim8]
8. An electronic circuit as claimed in any one of claims 1 to 7, wherein said 1 th inverter circuit and said 2 th inverter circuit each have a 1FET , th source connected to a 1 th power supply line, drain connected to an output node, The gate is connected to the input node; the 2FET , th source of the channel of the 2 th conductivity type opposite to the 1 th conductivity type is connected to the 2 th supply line, drain of the supply voltage supplied between the 1 th supply line and the 1 th supply line is connected to the intermediate node, The gate is connected to the aforementioned input node; the 3FET , th source of the channel of the 2 th conductivity type is connected to the aforementioned intermediate node, the drain is connected to the aforementioned output node, the gate is connected to the aforementioned input node; and 4FET , One of the source and drain is connected to the aforementioned intermediate node, and the other of the aforementioned source and drain is connected to the control node, The gate of the aforementioned 1 th inverter circuit is connected to the input node, the output node, and the gate of the aforementioned 1 th inverter circuit. Any 1 nodes of the input node and the output node of the aforementioned 2 th inverter circuit, The gate of the aforementioned 2 th inverter circuit is connected to the input node, and the output node of the aforementioned 2 th inverter circuit. Any of the input node and the output node of the aforementioned 1 th inverter circuit, th 4FET , th FET , th 2 th FET , th When the gate is connected to an input node of the aforementioned 1 th inverter circuit or an output node of the aforementioned 2 th inverter circuit, is a channel of the 1 th conductivity type FET , the aforementioned 4FET , th inverter circuit. When the gate is connected to the output node of the aforementioned 2 th inverter circuit or the input node of the aforementioned 1 th inverter circuit, is a channel of the 2 th conductivity type FET , when the gate is connected to the input node of the aforementioned 2 th inverter circuit or the output node of the aforementioned 1 th inverter circuit, is a channel of the 1 th conductivity type FET.

[claim9]
9. The electronic circuit of claim 8, wherein a fixed bias voltage is applied to the control nodes of the aforementioned 1 th inverter circuit and the aforementioned 2 th inverter circuit, The aforementioned 1 th inverter circuit and the aforementioned 2 th inverter circuit become the aforementioned 1 th mode when supplied with the aforementioned 1 th power supply voltage, and become the aforementioned 2 th mode when supplied with the aforementioned 2 th power supply voltage.

[claim10]
10. A bi-stable circuit, having a 1 th inverter circuit, a 2 th inverter circuit, a 1 th memory node, and a 2 th memory node, said 1 th inverter circuit and said 2 th inverter circuit each having a 1FET , th source connected to a 1 th power supply line, and a drain connected to an output node, and a gate connected to an input node; The 2FET , th source of the 2 th conductivity type channel opposite the aforementioned 1 th conductivity type is connected to the 2 th power supply line supplied with the supply voltage between the aforementioned 1 th power supply line, the drain is connected to the intermediate node, the gate is connected to the aforementioned input node; the 3FET , th source of the 2 th conductivity type channel is connected to the aforementioned intermediate node, the drain is connected to the aforementioned output node, the gate is connected to the aforementioned input node; And 1 The 4FET , th source and drain of a channel of the conductivity type are connected to the aforementioned intermediate node, the aforementioned source and the aforementioned drain are connected to the control node, the aforementioned 1 th memory node is connected to the output node of the aforementioned 1 th inverter circuit and the aforementioned 2 th inverter circuit, the aforementioned 2 th memory node is connected to the input node of the aforementioned 1 th inverter circuit and the aforementioned 2 th inverter circuit, The gate of the 4FET th of the aforementioned 1 th inverter circuit is connected to the input node of the aforementioned 1 th inverter circuit or the output node of the aforementioned 2 th inverter circuit, The gate of the 4FET th of the aforementioned 2 th inverter circuit is connected to the input node of the aforementioned 2 th inverter circuit or the output node of the aforementioned 1 th inverter circuit.

[claim11]
11. An electronic circuit, having a bistable circuit; as claimed in claim 10 and a power supply circuit, for switching said power supply voltage to a 1 th voltage and a 2 th voltage to supply, said 1 th voltage being a voltage at which said bistable circuit can write and read data, said 2 th voltage being a voltage lower than said 1 th voltage and said bistable circuit being capable of holding data.

[claim12]
12. The electronic circuit, of claim 11 wherein when said power supply circuit supplies any one of said 1 th voltage and said 2 th voltage to said bistable circuit, a fixed bias voltage is also supplied to said control node.

[claim13]
13. The electronic circuit, of claim 12 wherein said fixed bias voltage is a bias voltage between a voltage supplied to said 1 th power supply line and a voltage supplied to said 2 th power supply line.

[claim14]
14. The electronic circuit, of claim 12 wherein said fixed bias voltage is closer to a voltage of said 2 th power supply line than an intermediate voltage of said 1 th power supply line when said 1 th voltage is supplied to said 2 th power supply line

[claim15]
15. An electronic circuit as claimed in claim 11, provided with a control circuit, said control circuit being provided with a control circuit, said control node, said control circuit being provided with a low level and a higher level than said low level when said power circuit supplies said 1 th voltage and 2 voltage, respectively. When the aforementioned No. 4FET is N channel FET, when the aforementioned power supply circuit supplies the aforementioned No.1 voltage and 2 voltage, a high level and a lower level than the aforementioned high level are supplied to the aforementioned control node, respectively.

[claim16]
16. An electronic circuit, having a bistable circuit and a power supply circuit, said bistable circuit having a 1 -th inverter circuit, a 2 -th inverter circuit, a 1 -th memory node, and a 2 -memory node, said 1 -th inverter circuit and said 2 -th inverter circuit each having a: -th inverter circuit. The 1FET , th source of the 1 th conductivity type channel is connected to the 1 th power line, the drain is connected to the output node, the gate is connected to the input node; and the 2FET , th source of the 2 th conductivity type channel of the 1 th conductivity type is connected to the 2 th power line, which is supplied with the supply voltage between the 1 th power line and the 1 th power line. Drain connected to intermediate node, gate connected to said input node; 3FET , source connected to said intermediate node, drain connected to said output node, gate connected to said input node; And 4FET , One of the source and drain is connected to the aforementioned intermediate node, The other of the aforementioned source and drain is connected to the control node, The aforementioned 1 th memory node is connected to an output node of the aforementioned 1 th inverter circuit and to an input node of the aforementioned 2 th inverter circuit, The aforementioned 2 th memory node is connected to an input node of the aforementioned 1 th inverter circuit and an output node of the aforementioned 2 th inverter circuit, The gate of the aforementioned 1 th inverter circuit is connected to an input node of the aforementioned 1 th inverter circuit, and the gate of the aforementioned 1 th inverter circuit is connected to an output node of the aforementioned 1 th inverter circuit. The output node, the input node of the aforementioned 2 th inverter circuit and any 1 nodes of the output node, The gate of the aforementioned 2 th inverter circuit is connected to the input node, the output node, and the output node of the aforementioned 2 th inverter circuit. Any one of the input node and the output node of the aforementioned 1 th inverter circuit, The aforementioned power supply circuit switches the aforementioned power supply voltage into a 1 th voltage and a 2 th voltage for supplying, The aforementioned 1 th voltage is a voltage at which the aforementioned bistable circuit can write and read data, The aforementioned 2 th voltage is a voltage lower than the aforementioned 1 th voltage and the aforementioned bistable circuit can hold data, When the aforementioned power supply circuit supplies any of the aforementioned 1 th voltage and the aforementioned 2 th voltage to the aforementioned bistable circuit, a fixed bias voltage is also supplied at the aforementioned control node.

[claim17]
17. The electronic circuit, of claim 16 wherein said power supply circuit when switching said power supply voltage to said 1 th voltage and said 2 th voltage, supplies a certain 3 th voltage to said 2 th power supply line, and switches the voltage to said 1 th power supply line to 4 th voltage and 5 th voltage, respectively.

[claim18]
18. The electronic circuit, of claim 17 wherein said fixed bias voltage is a bias voltage between said 3 th voltage and said 4 th voltage.

[claim19]
19. The electronic circuit as claimed in any one of claims 16 to 18, wherein the 4FET , th 4FET , th, th FET , of the aforementioned 2 st inverter circuit being a channel of the 1 th conductivity type when a gate is connected to an output node of the aforementioned 2 th inverter circuit or an input node of the aforementioned 1 th inverter circuit, of a channel of the 2 th conductivity type FET , when a gate is connected to an input node of the aforementioned 2 th inverter circuit or an output node of the aforementioned 1 th inverter circuit, of a channel of the 1 th conductivity type.

[claim20]
20. An electronic circuit, having an array of: cells, having a plurality of memory cells having bistable circuits and non-volatile elements, said bistable circuits being each memory cell to store data in a volatile manner, The aforementioned non-volatile elements are non-volatile to store the data stored in the aforementioned bistable circuit, and to store the data that has been stored in a non-volatile manner back to the aforementioned bistable circuit; and control circuit, when the aforementioned cell array power supply is turned off, Whether or not the aforementioned plurality of memory cells are overwritten in a volatile manner, or not the 1 th or 1 th memory cell power supplies stored in a non-volatile manner are switched off, and the storing action is performed, after the aforementioned 1 th memory cell power supply is switched off, The remaining 1 of the plurality of memory cells or the 2 th memory cell, stores the data that has been stored in the bi-stable circuit in a volatile manner to the non-volatile elements, and then turns off the 2 th memory cell power supply.

[claim21]
21. An electronic circuit as claimed in claim 20, wherein said array of cells is a plurality of blocks divided into blocks containing at least 2 memory cells per block, said control circuit being adapted to extract from said plurality of blocks, whether or not memory cells within said block are rewritten in a volatile manner, None of the 1 th or 1 th blocks, stored in a non-volatile manner and the aforementioned 1 th or 1 th block power cut, After the aforementioned 1 th or 1 th block power cut, storage actions are performed in the remaining of the aforementioned plurality of blocks 1 or in the memory cells within the 2 th block, and the 2 th block power cut off where the storage action has ended.

[claim22]
22. The electronic circuit of claim 21, wherein said control circuit is a memory cell in said 1 or 2 th block after all of said 1 or 1 th block power has been switched off,.

[claim23]
23. An electronic circuit as claimed in claim 21 or 22, provided with a memory circuit, said memory circuit being arranged outside said array of cells, and memory displaying information of said 1 or 1 th block received from an external circuit, said control circuit extracting said 1 or 1 th block according to said information,.

[claim24]
24. The electronic circuit as claimed in claim 21 or 22, wherein said control circuit is a block that extracts from said plurality of blocks a block that is not stored in a non-volatile manner regardless of whether a memory cell within the block is written in a volatile manner, and no memory cell within the block is written in a volatile manner, As the aforementioned 1 or 1 th block, and cutting off the aforementioned 1 or 1 th block power, After cutting off the aforementioned 1 or 1 th block power, a storage action is performed in the remaining 1 or 2 th block of the aforementioned plurality of blocks, and a 2 th block power supply having the storage action terminated is switched off.
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • SUGAHARA SATOSHI
  • KITAGATA DAIKI
  • YAMAMOTO SHUICHIRO
国際特許分類(IPC)
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