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Non-volatile memory device and method for operating same

外国特許コード F210010526
整理番号 K203P35TW
掲載日 2021年7月30日
出願国 台湾
出願番号 109119037
公報番号 202107464
出願日 令和2年6月5日(2020.6.5)
公報発行日 令和3年2月16日(2021.2.16)
優先権データ
  • 特願2019-146870 (2019.8.8) JP
発明の名称 (英語) Non-volatile memory device and method for operating same
発明の概要(英語) This non-volatile memory device comprises a plurality of non-volatile memory elements. Each of the non-volatile memory elements is provided with: a channel layer containing a metal oxide; a ferroelectric layer that contains hafnium oxide and that abuts the channel layer; and a gate electrode that faces the channel layer across the ferroelectric layer, wherein the channel layer has a channel length of 1 [mu]m or less. The metal oxide may be IGZO. The channel layer may have a film thickness of less than 10 nm. Further, the ferroelectric layer may have a film thickness of 5-20 nm.
従来技術、競合技術の概要(英語) Background of the Invention]
One embodiment of the present invention relates to non-volatile memory elements. In particular, with respect to a non-volatile memory element of the electrocrystal type using a ferroelectric body as a gate insulating layer ( Ferroelectric Field Effect Transistor : the following is indicated as " FeFET ".).
[Prior Art]
In recent years, with the higher order of semiconductor systems, information communication has become necessary in a wide variety of fields of everyday life. Implementation of so-called object networking ( IoT , Internet of Things ), It becomes necessary for high-speed and mass communication of information between a computer (such as a server) and a home appliance (also referred to as an edge device). Yes, For household appliances, non-volatile memory is needed as high speed and mass storage memory. Further, With miniaturization of household electricity products, low consumption of electricity has been strongly required in non-volatile memory.
In the expansion of the demand for non-volatile memory, previously known ferroelectric memories are bathing under new spotlights. Commercially available ferroelectric memory uses components that switch field effect transistors ( FET ) and make the ferroelectric capacitor cells. In this element, although a piezoelectric ceramic such as PZT (lead zirconate titanate) is used as the ferroelectric material, thinning PZT has the so-called dimensional effect of losing ferroelectric. So, the densification of flash memory has progressed, and the densification of ferroelectric memory has hardly progressed.
In this case, in 2011 it was published that materials doped with elements such as Si to hafnium oxide exhibit ferroelectric properties in thin films, this dimensional effect is much less than the well known PZT and so on. Ferroelectric memory using such hafnium oxide materials, has the features of high integration with the CMOS process, rapid erase/programming speed, and low power consumption at low voltage operation. It is therefore, recently actively developing FeFET (for example, Non-Patent Document 1 and Non-Patent Document 2 ) using hafnium oxide based materials as gate insulating layers. And, In order to store further mass storage of memory, it has also been proposed to bulk a plurality of FeFET memories in a three-dimensional structure for low power consumption at high density (e. g., Non-Patent Document 3 ).
'Non-patent document' Non-patent document 1 : Min-Kyu Kim Jang-Sik Lee , " Ferroelectric Analog Synaptic Transistors " , [ online ] , 2019 30 Access ] , Network, 13 2 (URL : https://pubs.acs.org/doi/abs/10.1021/acs.nanolett . 9b00180 ( 2019) Non-patent Document 2 : Yuxing Li, Renrong Liang, Jiabin Wang, Ying Zhang, He Tian, Houfang Liu, Songlin Li, Weiquan Mao, : Yuxing Li Yu Pang, Yutao Li, Yi Yang, Tian-Ling Ren , " A Ferroelectric Thin Film Transistor Based on Annealing-Free HfZrO Film " , 2017 , IEEE Journal of the Electron Devices Society , Volume 5 , Page ( s ) : 378-383 , ( 2017) Non-Patent Document 3 : K. Florent. M. Pesic, A. Subirats, K. Banerjee, S. Lavizzari, A. Arreghini, L. Di Piazza, G. Potoms, F. Sebaai, S. R. C. McMitchell, M. Popovici, G. Groeseneken, J. Van Houdt , " Vertical Ferroelectric HfO2FET based on 3 -D NAND Architecture : Towards Dense Low-Power Memory " , 2018 IEEE International Electron Devices Meeting (IEDM ) , Page ( s ) : 2.5.1-2.5.4 , ( 2018)
特許請求の範囲(英語) [claim1]
1. A non-volatile memory device, which is a non-volatile memory device comprising a plurality of non-volatile memory elements, wherein each non-volatile memory element has: a via layer comprising a metal oxide, a ferroelectric layer comprising hafnium oxide in contact with said via layer, and a gate layer comprising hafnium oxide in contact with said gate layer. 1 th gate electrode which mediates the aforementioned ferroelectric layer and is opposite to the aforementioned channel layer, an insulating layer which mediates the aforementioned channel layer and is opposite to the aforementioned ferroelectric layer,, and a 2 th gate electrode which mediates the aforementioned insulating layer and is opposite to the aforementioned channel layer.

[claim2]
2. The non-volatile memory device, of claim 1 wherein said channel layer has a channel length of less than 1 um.

[claim3]
3. The non-volatile memory device, as claimed in claim 1 or 2 wherein said insulating layer comprises silicon oxide.

[claim4]
4. The non-volatile memory device, as claimed in claim 1 or 2, wherein the ratio of the film thickness of the insulating layer to the film thickness of the channel layer is 1.0 or more and 1.8 or less.

[claim5]
5. A non-volatile memory device, is a non-volatile memory device comprising a plurality of non-volatile memory elements, wherein each non-volatile memory element has: a channel layer comprising a metal oxide, a ferroelectric layer comprising hafnium oxide in contact with said channel layer, and a gate electrode that mediates said ferroelectric layer and is opposite said channel layer, wherein said channel layer has a channel length of less than 1 um.

[claim6]
6. The non-volatile memory device, of claim 5 wherein said channel layer has a channel length of less than 50 nm.

[claim7]
7. The non-volatile memory device, of claim 2, 5, or 6 wherein said metal oxide is IGZO, ITO, IZO, or ITZO.

[claim8]
8. The non-volatile memory device of claim 2, 5 or 6 wherein the film thickness of the channel layer is not up to 10 nm.

[claim9]
9. The non-volatile memory device, of claim 2, 5 or 6 wherein said ferroelectric layer has a film thickness of 5 nm or more and 20 nm or less.

[claim10]
10. A method of operation of a non-volatile memory device, which is a method of operation of a non-volatile memory device comprising a plurality of non-volatile memory elements, wherein each non-volatile memory element has: a channel layer comprising a metal oxide, a ferroelectric layer comprising hafnium oxide in contact with said channel layer, 1 th gate electrode intermediate the aforementioned ferroelectric layer and opposite the aforementioned channel layer, insulating layer intermediate the aforementioned channel layer and opposite the aforementioned ferroelectric layer, 2 th gate electrode intermediate the aforementioned insulating layer and opposite the aforementioned channel layer, source electrode in contact with the aforementioned channel layer, And a drain electrode spaced from said source electrode and in contact with said channel layer; said non-volatile memory device having: at least a portion of said plurality of non-volatile memory elements, a gate voltage applying a negative voltage to said 1 th gate electrode and an erase operation applying a 1 th drain voltage to said drain electrode; And a programming operation for applying a gate voltage of a positive voltage to said 1 th gate electrode and a 2 th drain voltage to said 1 th drain electrode at least a portion of said plurality of non-volatile memory elements; wherein said 1 th drain voltage is a positive voltage.

[claim11]
11. A method of operating a non-volatile memory device, which is a method of operating a non-volatile memory device comprising a plurality of non-volatile memory elements, wherein each non-volatile memory element has: a channel layer comprising a metal oxide; A ferroelectric layer comprising hafnium oxide in contact with said channel layer, a gate electrode intermediate said ferroelectric layer and opposite said channel layer, a source electrode in contact with said channel layer, and a drain electrode spaced from said source electrode and in contact with said channel layer, Wherein the channel length of the aforementioned channel layer is 1 μm or less; The aforementioned non-volatile memory device is operated by a method having: a gate voltage of negative voltage applied to at least a portion of the aforementioned plurality of non-volatile memory elements, and an erase operation of applying a 1 th drain voltage to the aforementioned gate electrode; And a programming operation for applying a gate voltage of a positive voltage to said gate electrode and a 2 th drain voltage to said drain electrode at least a portion of said plurality of non-volatile memory elements, wherein said 1 th drain voltage is a positive voltage.

[claim12]
12. The method of operation of a non-volatile memory device as claimed in claim 10 or 11, wherein the aforementioned 2 th drain voltage is a positive voltage or 0 V.

[claim13]
13. A method of operating a non-volatile memory device as claimed in claim 10 or 11 wherein said 1 th drain voltage is greater than said 2 th drain voltage.
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • KOBAYASHI MASAHARU
  • MO FEI
  • HIRAMOTO TOSHIRO
国際特許分類(IPC)
参考情報 (研究プロジェクト等) PRESTO Innovative Nano-electronics through Interdisciplinary Collaboration among Material, Device and System Layers AREA
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