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Multiprocessor system and multiprocessor system synchronization method

Foreign code F110002411
File No. 167-CN
Posted date Feb 3, 2011
Country China
Application number 200980103004
Gazette No. 101925881
Gazette No. 101925881
Date of filing Jan 23, 2009
Gazette Date Dec 22, 2010
Gazette Date Jun 5, 2013
Priority data
  • P2008-015028 (Jan 25, 2008) JP
Title Multiprocessor system and multiprocessor system synchronization method
Abstract

Each of processor CPU (#0 to #7) includes a barrier write register BARW and a barrier read register BARR. A dedicated wiring block WBLK3 is used to connect the respective BARW to the respective BARR. For example, 1-bit BARW of CPU #0 is connected via the WBLK3 to the first bit of the respective 8-bit BARR contained in the CPU (#0 to #7) while 1-bit BARW of the CPU #1 is connected via the WBLK3 to the second bit of the respective 8-bit BARR contained in the CPU (#0 to #7). For example, the CPU #0 writes information into the BARW of itself so as to report a synchronization waiting state to the other CPU (#1 to #7) and reads the BAR of itself so as to recognize whether the other CPU (#1 to #7) are in the synchronization waiting state. This eliminates the need of a special dedicated command for the barrier synchronization process and increases the processing speed.

  • Applicant
  • UNIV WASEDA
  • Inventor
  • KASAHARA HIRONORI,
  • KIMURA KEIJI,
  • ITO MASAYUKI,
  • KAMEI TATSUYA,
  • HATTORI TOSHIHIRO
IPC(International Patent Classification)
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