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Memory management method and information processing device implementing the method

Foreign code F110002416
File No. 138-GB
Posted date Feb 3, 2011
Country United Kingdom of Great Britain and Northern Ireland
Application number 0914592
Gazette No. 2459802
Gazette No. 2459802
Date of filing Feb 27, 2008
Gazette Date Nov 11, 2009
Gazette Date Jan 4, 2012
Priority data
  • P2007-050269 (Feb 28, 2007) JP
Title Memory management method and information processing device implementing the method
Abstract

Provided is a method for managing a memory storage region used by a processor. The processor is connected to a memory for storing data used upon execution of a task. The storage region of the memory is divided into a plurality of blocks of different sizes. A block of the size appropriate for the data used upon execution of the task is selected. The data used upon execution of the task is stored in the selected block so as to effectively arrange the data in the memory.

  • Applicant
  • WASEDA UNIVERSITY
  • Inventor
  • HIRONORI KASAHARA,
  • KEIJI KIMURA,
  • HIROFUMI NAKANO,
  • TAKUMI NITO,
  • TAKANORI MARUYAMA,
  • TSUYOSHI MIURA,
  • TOMOHIRO TAGAWA
IPC(International Patent Classification)
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