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ASSOCIATED MEMORY achieved

Foreign code F110002470
File No. 5016PCT
Posted date Mar 8, 2011
Country WIPO
International application number 2007JP056498
International publication number WO 2007/119540
Date of international filing Mar 27, 2007
Date of international publication Oct 25, 2007
Priority data
  • P2006-101106 (Mar 31, 2006) JP
Title ASSOCIATED MEMORY achieved
Abstract An associated memory is provided with features of suppression of power consumption and a device structure to be simplified with a small installing area while maintaining high speed retrieval. The associated memory is comprised of a simplified function operation unit made of an LUT coupled logic circuit of a simplified CAM function (g) in which an invalid output of the CAM function (f) is replaced by don't-care, an auxiliary memory in which a reverse function (f-1) of the CAM function (f) is stored, and a consistency judging means for judging whether an output of an LUT operating means is consistent with an output of the CAM function (f), wherein the LUT operating means outputs an operated value (tentative index value) of the simplified CAM function (g) for input data, the auxiliary memory outputs the reverse function (f-1) of the tentative index value when the tentative index value is input, and the judging means compares the input date with the reverse function (f-1) and outputs an output value of the LUT operating means when the input data and the output value are consistent with each other but, otherwise, outputs an invalid signal.
Scope of claims (In Japanese)
【請求項1】入力データに対しそのデータに対応する固有のインデックスを出力する連想記憶メモリであって、入力データに対しそのデータに対応する固有のインデックスを出力する関数(以下「CAM(Content Addressable Memory)関数」という。)fの無効出力値をドント・ケアで置き換えた関数(以下「簡略化CAM関数」という。)gを表すLUT結合論理回路又はPLAにより構成された簡略化関数演算部と、前記CAM関数fの逆関数f-1が記憶された補助メモリと、前記LUT演算手段の出力値がCAM関数fの出力に一致するか否かを判定する一致判定手段と、を備え、前記LUT演算手段は、前記入力データに対して前記簡略化CAM関数gの演算値(以下「仮インデックス値」という。)を前記補助メモリの読み出しアドレスとして出力し、前記補助メモリは、前記仮インデックス値が読み出しアドレスとして入力されると、その仮インデックス値に対しする逆関数f-1の値を出力し、前記判定手段は、前記入力データと前記補助メモリが出力する逆関数f-1の値とを比較して、両者が一致する場合は前記LUT演算手段の出力値を出力し、それ以外の場合は無効信号を出力することを特徴とする連想メモリ。

【請求項2】前記LUT結合論理回路は、LUTカスケード論理回路であることを特徴とする請求項1記載の連想メモリ。

【請求項3】前記LUT結合論理回路は、pq回路網であることを特徴とする請求項1記載の連想メモリ。
  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • KYUSHU INSTITUTE OF TECHNOLOGY
  • Inventor
  • SASAO, Tsutomu
IPC(International Patent Classification)
Specified countries AE(UTILITY MODEL),AG,AL(UTILITY MODEL),AM(PROVISIONAL PATENT)(UTILITY MODEL),AT(UTILITY MODEL),AU,AZ(UTILITY MODEL),BA,BB,BG(UTILITY MODEL),BH,BR(UTILITY MODEL),BW,BY(UTILITY MODEL),BZ(UTILITY MODEL),CA,CH,CN(UTILITY MODEL),CO(UTILITY MODEL),CR(UTILITY MODEL),CU(INVENTOR'S CERTIFICATE),CZ(UTILITY MODEL),DE(UTILITY MODEL),DK(UTILITY MODEL),DM,DZ,EC(UTILITY MODEL),EE(UTILITY MODEL),EG(UTILITY MODEL),ES(UTILITY MODEL),FI(UTILITY MODEL),GB,GD,GE(UTILITY MODEL),GH,GM,GT,HN,HR(CONSENSUAL PATENT),HU(UTILITY MODEL),ID,IL,IN,IS,JP(UTILITY MODEL),KE(UTILITY MODEL),KG(UTILITY MODEL),KM,KN,KP(INVENTOR'S CERTIFICATE)(UTILITY MODEL),KR(UTILITY MODEL),KZ(PROVISIONAL PATENT)(UTILITY MODEL),LA,LC,LK,LR,LS(UTILITY MODEL),LT,LU,LY,MA,MD(UTILITY MODEL),MG,MK,MN,MW,MX(UTILITY MODEL),MY(UTILITY-INNOVATION),MZ(UTILITY MODEL),NA,NG,NI(UTILITY MODEL),NO,NZ,OM,PG,PH(UTILITY MODEL),PL(UTILITY MODEL),PT(UTILITY MODEL),RO,RS(PETTY PATENT),RU(UTILITY MODEL),SC,SD,SE,SG,SK(UTILITY MODEL),SL(UTILITY MODEL),SM,SV,SY,TJ(UTILITY MODEL),TM(PROVISIONAL PATENT),TN,TR(UTILITY MODEL),TT(UTILITY CERTIFICATE),TZ,UA(UTILITY MODEL),UG(UTILITY CERTIFICATE),US,UZ(UTILITY MODEL),VC(UTILITY CERTIFICATE),VN,ZA,ZM,ZW,EP(AT,BE,BG,CH,CY,CZ,DE,DK,EE,ES,FI,FR,GB,GR,HU,IE,IS,IT,LT,LU,LV,MC,MT,NL,PL,PT,RO,SE,SI,SK,TR),OA(BF(UTILITY MODEL),BJ(UTILITY MODEL),CF(UTILITY MODEL),CG(UTILITY MODEL),CI(UTILITY MODEL),CM(UTILITY MODEL),GA(UTILITY MODEL),GN(UTILITY MODEL),GQ(UTILITY MODEL),GW(UTILITY MODEL),ML(UTILITY MODEL),MR(UTILITY MODEL),NE(UTILITY MODEL),SN(UTILITY MODEL),TD(UTILITY MODEL),TG(UTILITY MODEL)),AP(BW,GH,GM,KE,LS,MW,MZ,NA,SD,SL,SZ,TZ,UG,ZM,ZW),EA(AM,AZ,BY,KG,KZ,MD,RU,TJ,TM)
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