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Amorphous oxide and thin film transistor achieved

Foreign code F110003744
File No. E06015US3
Posted date Jul 4, 2011
Country United States of America
Application number 98496011
Gazette No. 20110101352
Gazette No. 9269826
Date of filing Jan 5, 2011
Gazette Date May 5, 2011
Gazette Date Feb 23, 2016
International application number JP2005003273
International publication number WO2005088726
Date of international filing Feb 28, 2005
Date of international publication Sep 22, 2005
Priority data
  • P2004-071477 (Mar 12, 2004) JP
  • P2004-325938 (Nov 10, 2004) JP
  • 2005US-10592431 (Feb 28, 2005) US
  • 2005WO-JP03273 (Feb 28, 2005) WO
Title Amorphous oxide and thin film transistor achieved
Abstract (US9269826)
The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide.
In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 1018/cm3, and a thin film transistor using such an amorphous oxide.
In a thin film transistor having a source electrode 6, a drain electrode 5, a gate electrode 4, a gate insulating film 3, and a channel layer 2, an amorphous oxide having an electron carrier concentration less than 1018/cm3 is used in the channel layer 2.
Scope of claims [claim1]
1. A thin film transistor device comprising: a drain electrode;
a source electrode;
a channel layer contacting the drain electrode and the source electrode, wherein the channel layer is formed of an amorphous InxSn1-xOxide (0.8 <= x <= 0.9) consisting of SnO2 in the presence of In2O3 as a host oxide, further the channel layer is prepared by a sputtering method or a pulsed laser deposition method using a In2O3 -- SnO2 polycrystalline sinter as a target in an atmosphere containing oxygen gas, and
the channel layer having a transparent, semi-insulating property represented by the electron mobility is more than 1 cm2/(V.sec) and the electron carrier concentration is 1018/cm3 or less as measured by Hall-effect measurement at room temperature;
a gate electrode; and
a gate insulating film positioned between the gate electrode and the channel.
  • Inventor, and Inventor/Applicant
  • HOSONO HIDEO
  • HIRANO MASAHIRO
  • OTA HIROMICHI
  • KAMIYA TOSHIO
  • NOMURA KENJI
  • CANON
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • TOKYO INSTITUTE OF TECHNOLOGY
IPC(International Patent Classification)
Reference ( R and D project ) ERATO HOSONO Transparent ElectroActive Materials AREA
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